14-bit shift register vhdl

[jimmykk]

Hi
i am writing code for shift register with serial out data. i am having some code problem, when i change the STEP to value other than 14398, i dont get any output. basically STEP increases with every clock and when it equals certain count, it should output data serially.
here is my code:-

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity light is
port(
CLOCK_50 : in std_logic;
reset : in std_logic;
enable : in std_logic;
GPIO_1 : inout std_logic_vector(35 downto 0);
GPIO_0 : out std_logic_vector(35 downto 0)
 
) ; 
end light;
 
 
 
architecture logicfunction of light is
type state_type is (wait_state,shift_state);
SIGNAL present_state : state_type;
signal turn    : std_logic := '0';
signal RISINGEDGE     : std_logic := '1';
signal count : integer range 0 to 10 :=0;  -- register that keeps the count
signal data : std_logic := '0';
signal shift_reg : std_logic_vector(13 downto 0) := (Others => '0'); 
--signal dac_cnt_half : std_logic_vector(13 downto 0)   := "01110000011111";
signal dac_cnt_max : std_logic_vector(13 downto 0)      := "11100000111110";
begin
 
GPIO_1(1) <= turn;
clk_div: process(CLOCK_50)
 
begin
if (rising_edge(CLOCK_50)) then
 
if(count = 10) then    --*
turn <= turn XOR '1';
RISINGEDGE <= RISINGEDGE XOR '1';
count <= 0;
else
count <= count + 1;
end if;
end if;
end process clk_div;
 
 
 
MAIN: process(turn,reset)
variable shift_counter : integer := 0;
variable step : integer range 0 to 100000 := 0;
begin
if (reset = '1') then
shift_reg <= (others => '0');
present_state <= wait_state;
shift_counter := 0;
 
elsif(turn'event and turn = '1') then
 
case present_state is
 
when wait_state =>
shift_counter := 0;
shift_reg <= dac_cnt_max;  
GPIO_1(2) <= '0';
 
if (step = 14398) then
step := 0;
present_state <= shift_state;
else
step := step + 1;
present_state <= wait_state;
end if;
 
 
when shift_state =>
shift_counter := shift_counter + 1;
GPIO_1(2) <= shift_reg(0);
shift_reg <= data & shift_reg(13 downto 1);
if (shift_counter >= 13) then
present_state <= wait_state;
else 
present_state <= shift_state;
end if;
end case;
end if; 
end process MAIN;
end logicfunction;

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Anybody which can explain and help me where i am doing wrong

 

[ads-ee]

Why are you generating a turn clock, turn should be an enable signal and the MAIN process should be run off the CLOCK_50. Generating clocks in an FPGA's fabric is not advised, due to problems in routing the clock from logic resources.

I'm not a VHDL expert, but I wonder if the problem has to do with using variables for shift_counter and step. I don't see why you can't use a signal for either of those counters. Unless you really know what hardware a variable will describe I would avoid them altogether.

As a suggestion I would not use = for comparing counter terminal values. If the counter accidentally ends up with a count value beyond the terminal value it will continue counting till it rolls over.

 

[TrickyDicky]

First question - where is your testbench?
Second - like ads-ee - why are you generating clocks?

I also advise you use only signals, no variables. There is nothing you can do with a variable you can do with a signal (and you're safer using a signal).

 

[jimmykk]

ok....i got this that i need to synchronize my processes with the same system clock , so i will use just one clock and divide to to the desired range and use step and shift_counter as signals. but my main problem is that i want to get a specific voltage out (between 0 and 3.3V) whenever step equals a particular count and i want that count as output voltage like for 14398, the output voltage should be 2.9 V and for step =12412, voltage should be 2.5V, IF this makes sense.

 

[TrickyDicky]

Doesnt really make sense as I have no idea what component you are using.
The easiest thing for you would be to make a testbench, so that with a known set of inputs and outputs, you can check your design is working correctly.

 

[jimmykk]

i am using a 14-bit spi dac AD5641 acting as a shift register to get analog voltage

 

[FvM]

Using divided clocks is bad design practice, as said, but it doesn't cause problems for an isolated entity that doesn't interface with other design units as long as the divided clock is a glitch-free registered signal.

To work as a SPI master, your design should be supplemented with a slave select ("SYNC") signal, operated according to AD5641 specification.

I don't a reason why the step won't work for arbitrary delays up to the number range. Although using signals for the counter would be the regular VHDL way, variables do work in this specific case. A possible disadvantage can be seen in the below snippet where the comparison refers to the updated value shift_counter + 1 which possibly creates more complex logic than required for a signal due to the "blocking" behaviour of variable assignments. This can cause timing issues in real complex logic designs.

shift_counter := shift_counter + 1;
GPIO_1(2) <= shift_reg(0);
shift_reg <= data & shift_reg(13 downto 1);
if (shift_counter >= 13) then