Clock Skew Minimization

[alchemist1]

Hi,

Why do we reduce clock skew in clock tree synthesis? can anyone give some equations and explanation?


thankz

 

[shiv_emf]

understand the meaning of skew !! u will get ur ans. do u know the purpose of clock tree?

 

[alchemist1]

hi shiv_emf,

wat is basically the difference bt

Tcp >= Td + Tskew + Tsu + Tcq


and


Tcp >= Td - Tskew + Tsu + Tcq.


please give me answers and not comments

thanks

 

[shiv_emf]

hi shiv_emf,

wat is basically the difference bt

Tcp >= Td + Tskew + Tsu + Tcq


and


Tcp >= Td - Tskew + Tsu + Tcq.


please give me answers and not comments

thanks

When clock direction is same as data flow then delay between launching clock and capture clock is positive skew otherwise negative skew.

tell me if u want more details..

 

[lordsathish]

hi shiv_emf,

wat is basically the difference bt

Tcp >= Td + Tskew + Tsu + Tcq


and


Tcp >= Td - Tskew + Tsu + Tcq.


please give me answers and not comments

thanks

In the first case the clock direction is opposite to the data flow direction.
And in th second case the clock and the data are in the same direction...

 

[alchemist1]

hi,

i do understand that positive skew aids setup but may lead to hold violation if it is let to exceed above "skew + thold <tcqmin + tcombmin." and also i understood wat negative skew is.

But my question is that when we consider clock tree mostly we will analyse for positive skew and when we consider positive skew why do we minimize it as much as possible as increase in skew reduces the clock period which ensures max frequency according to the following eq,

Tclock >= Tcq + Tcomb + Tsetup - Tskew

What do we exactly achieve by minimizing skew in clock tree. i may not be fit for physical design right nw. but wanna b. so kindly throw some light on the issue. If possible please upload some materials on clock tree

thankz

 

[deh_fuhrer]

hi,

i do understand that positive skew aids setup but may lead to hold violation if it is let to exceed above "skew + thold <tcqmin + tcombmin." and also i understood wat negative skew is.

thankz

Questions as well as the answer.....

Simple you don't want skew at all in the clock tree, positive skew might help setup but it'll destroy hold and vice versa.. Also, you can operate with setup violation by decreasing the clock frequency, but for hold violation....Throw away your chip.....It is as simple as that......
If you still need further clarification, please be specific and clear about your doubt...

Thanks...

 

[alchemist1]

thanks for the answers guys. as i told i got really upset bcoz of

Tcp >= Td + Tskew + Tsu + Tcq

and

Tcp >= Td - Tskew + Tsu + Tcq.

So the basic funda is that we need to minimize skew as much as possible to avoid hold violation and not bcoz we are analyzing from a negative skew angle. right?

 

[deh_fuhrer]

thanks for the answers guys. as i told i got really upset bcoz of

Tcp >= Td + Tskew + Tsu + Tcq

and

Tcp >= Td - Tskew + Tsu + Tcq.

So the basic funda is that we need to minimize skew as much as possible to avoid hold violation and not bcoz we are analyzing from a negative skew angle. right?

Skew is nothing....Forget about it for a time being....draw two flip-flop and try to analyze it what might be troubling you (your chip) if two flops are separated in chip, hence the clocks are shifted by a delay in both the flops....take both the directions, i.e. clock coming from right side to left (right flop to left), and then analyze for clock coming from left to right...Data direction is only from left to right for both the cases...Now check it for timing violation (draw window on the enabling edge of the flop around which data need to be stable).....


Check this file...Posted somewhere in edaboard but I forget the path so I am again uploading this file..... I hope moderators ignore this mistake...

 

[usaid]

Check this one....

 

[usaid]

Check these papers on clock tree synthesis......

 

[zhang2000]

thanks

 

[cihchenlin]

ha,learn so more,thanks