what is a duty cycle in a verilog hdl
hey !
check it this symbol and my simulation
tick_max output is 10% duty cycle of any input clock! is it ok??
the VHDL code is as below
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
entity M_counter is
generic (N: integer := 4;
M: integer := 10 );
port(
clk, reset: in std_logic;
q : out std_logic_vector ( N-1 downto 0);
max_tick: out std_logic
);
end M_counter;
Architecture arch_M of M_counter is
signal r_reg : unsigned ( N-1 downto 0);
signal r_next : unsigned ( N-1 downto 0);
-- register
begin
process(clk, reset)
begin
if (reset='1')then
r_reg<= (others=>'0');
elsif (clk'event and clk='1')then
r_reg<=r_next;
end if;
end process;
--next state logic
r_next<= (others=>'0') when r_reg = (M-1) else
r_reg+1;
--output logic
q<= std_logic_vector (r_reg);
max_tick <= '1'when r_reg=(M-1) else'0';
end arch_M;