10-bit ADC interfacing with spartan-3 fpga--verilog code

[uzi92]

hello.

i am trying to operate by robot for specific application with fpga spartan-3.i need to interface ADC with fpga.
please anyone could share a verilog code for interfacing ADC IC with FPGA spartan-3.its urgent.

 

[peterlarky]

What ADC are you using?

 

[uzi92]

MICROchip ADC IC.

 

[mrflibble]

MICROchip ADC IC.

You really don't want a solution do you? Post specific part numbers and links to datasheet you non-specific monkey! That gets you solutions faster.

 

[asraf]

here i provide you with my working ADC code together with it ucf file..try it..should be ok...
//////////////////////////ucf file////////////////////////////////////////////

NET "ad_conv" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "amp_cs" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "amp_dout" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
NET "amp_shdn" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "sf_ce0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;

NET "dac_clr" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "dac_cs" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

NET "fpga_init_b" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;

NET "spi_miso" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "spi_mosi" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "spi_sck" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "spi_ss_b" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

NET "reset" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;

NET "led[0]" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led[1]" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led[2]" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led[3]" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led[4]" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led[5]" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led[6]" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led[7]" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

//////////////////////////////////////////////////////////////////////////////////////////////////////////////



`timescale 1ns / 1ps


//////////////////////////////////////////////////////////////////////////////////
module test(clk,reset,spi_sck,amp_cs,spi_mosi,spi_miso,ad_conv,spi_ss_b,amp_cs,dac_cs,sf_ce0,fpga_init_b,amp_shdn,dac_clr,led);

input clk,reset;
input spi_miso;

output reg [7:0] led;
output reg spi_sck;
output reg amp_cs;
output reg spi_mosi;
output reg ad_conv;
output reg amp_shdn;
output reg dac_clr;

output reg spi_ss_b;
output reg dac_cs;
output reg sf_ce0;
output reg fpga_init_b;

reg [6:0] counter;////count spi_sck for period 100 cycles
reg [4:0] counter2;////count spi_sck for period 20 cycles
reg [5:0] counter3;////count spi_sck for period 34 cycles
reg [5:0] state;
reg [1:0] state2;
reg [7:0] data;
reg [13:0] data_adc1;//assume from data to spi_miso first to test
reg [13:0] data_adc2;
reg [3:0] kire;
reg [3:0] kire_amp_cs;
reg [2:0] kire_delay;
reg [3:0] kire_14bit;
reg [2:0] kire_adc;
reg enable1;
reg enable2;

reg [27:0] counter_led;
reg sclk;

initial
begin

amp_cs<=1;
spi_sck=0;
counter<=0;
counter2<=0;
counter3<=0;
data=8'b00110011;
data_adc1=14'b0;
data_adc2=14'b0;
kire<=4'd7;
kire_adc<=4'd0;
kire_14bit<=4'd13;
kire_amp_cs<=4'd0;
kire_delay<=0;
ad_conv<=0;
led<=0;
enable1<=0;
enable2<=0;

end

always@(posedge clk or posedge reset)
begin
spi_ss_b<=1;
dac_cs<=1;
sf_ce0<=1;
fpga_init_b<=1;
amp_shdn<=0;
dac_clr<=0;
end


/////////////////////////counter//////////////////////////////////
always@(posedge clk or posedge reset)
begin
if(reset)
begin
counter<=0;
end
else
begin
if(counter==7'd100)
begin
counter<=0;
end
else
begin
counter<=counter+1'b1;
end
end
end

/////////////////////////counter2//////////////////////////////////
always@(posedge clk or posedge reset)
begin
if(reset)
begin
counter2<=0;
end
else
begin
if(counter2==5'd20)
begin
counter2<=0;
end
else
begin
counter2<=counter2+1'b1;
end
end
end
////////////////////////////for slow clock/////////////////////


always@(posedge clk or posedge reset)
begin
if(reset)
counter_led<=0;
else begin
if(counter_led==28'd5000000)
counter_led<=0;
else
counter_led<=counter_led+1;
end
end


always@(posedge clk or posedge reset)
begin
if(reset)
sclk=0;
else if(counter_led==28'd5000000)
sclk=0;
else if(counter_led==28'd0)
sclk=1;
end

///////////////////////////////////////////////////////////////////

always@(posedge clk or posedge reset )
begin
if(reset)
begin
state<=0;
end
else
begin
case(state)

0:
begin
amp_cs<=1;
ad_conv<=0;
kire<=4'd7;
kire_adc<=4'd0;
counter3<=6'd0;
if(counter==7'd20)
state<=1;
else
state<=0;
end

1:
begin
amp_cs<=0;
spi_sck=0;
if(counter==7'd50)
state<=2;
else
state<=1;
end


2:

begin
spi_sck=1;
spi_mosi<=data[kire];//data for amplifier
if(counter==7'd100)
state<=3;
else
state<=2;
end


3:

begin
spi_sck=0;
kire<=kire-1'b1;
if(kire==4'd0)
state<=4;// dah habis kire untuk amplifier..gi buat adc pulak..
else
state<=1;
end


4:
begin
amp_cs<=0;
spi_sck=0;
if(counter==7'd50)
state<=5;
else
state<=4;
end

5:
begin
amp_cs<=1;
kire_amp_cs<=kire_amp_cs+1'b1;
if(kire_amp_cs==4'd10)
state<=6;
else
state<=5;
end



6:
begin

ad_conv<=1;
kire_adc<=kire_adc+1'b1;
if(kire_adc==4'd3)
state<=7;
else
state<=6;
end

7:
begin
ad_conv<=0;
spi_sck=0;
kire_adc<=kire_adc+1'b1;
if(kire_adc==4'd7)
state<=8;
else
state<=7;
end

8:
begin
kire_adc<=0;
counter3<=counter3+1'b1;
if(counter3==6'd2)
state<=11;
else
state<=9;
end


9:
begin
spi_sck=1;
if(counter2==5'd10)
state<=10;
else
state<=9;
end

10:
begin
spi_sck=0;
if(counter2==5'd20)
state<=8;
else
state<=10;
end

11:

begin
spi_sck=1;
//data_adc0[kire_14bit]<=spi_miso;
//spi_miso<=data_adc0[kire_14bit];
//enable1<=1;
if(counter2==5'd10)
state<=12;
else
state<=11;
end

12:
begin
spi_sck=0;
if(counter2==5'd20)
state<=13;
else
state<=12;
end

13:
begin
kire_14bit<=kire_14bit-1'b1;
counter3<=counter3+1'b1;
if(kire_14bit==0)
state<=14;
else
state<=11;
end

14:
begin
//enable1<=0;
kire_14bit<=4'd13;
spi_sck=1;
if(counter2==5'd10)
state<=15;
else
state<=14;
end

15:
begin
spi_sck=0;
if(counter2==5'd20)
state<=16;
else
state<=15;
end

16:
begin
counter3<=counter3+1'b1;
if(counter3==6'd18)
state<=17;
else
state<=14;
end

17:
begin

spi_sck=1;
//enable2<=1;
//spi_miso<=data_adc1[kire_14bit];
if(counter2==5'd10)
state<=18;
else
state<=17;
end

18:
begin
spi_sck=0;
if(counter2==5'd20)
state<=19;
else
state<=18;
end

19:
begin
kire_14bit<=kire_14bit-1'b1;
counter3<=counter3+1'b1;
if(kire_14bit==0)
state<=20;
else
state<=17;
end

20:
begin
//enable2<=0;
kire_14bit<=4'd13;
spi_sck=1;
if(counter2==5'd10)
state<=21;
else
state<=20;
end

21:
begin
spi_sck=0;
if(counter2==5'd20)
state<=22;
else
state<=21;
end

22:
begin
counter3<=counter3+1'b1;
if(counter3==6'd34)
state<=23;//state<=0;
else
state<=20;
end

23:
begin
ad_conv<=0;
counter3<=6'd0;
kire_adc<=kire_adc+1'b1;
if(kire_adc==4'd3)
state<=24;
else
state<=23;
end

24:
begin
ad_conv<=1;
spi_sck=0;
kire_adc<=kire_adc+1'b1;
if(kire_adc==4'd7)
state<=25;
else
state<=24;
end

25:
begin
kire_adc<=0;
ad_conv<=0;
kire_delay<=kire_delay+1'b1;
if(kire_delay==3'd7)
state<=26;
else
state<=25;
end

26://6
begin

//ad_conv<=1;
//kire_adc<=kire_adc+1'b1;
//if(kire_adc==4'd3)
state<=27;//7
//else
//state<=26;//6
end

27: //7
begin
//ad_conv<=0;
spi_sck=0;
//kire_adc<=kire_adc+1'b1;
//if(kire_adc==4'd7)
state<=28;//8
//else
//state<=27;//7
end

28://8
begin
kire_adc<=0;
counter3<=counter3+1'b1;
if(counter3==6'd2)
state<=31;//11
else
state<=29;//9
end


29://9
begin
spi_sck=1;
if(counter2==5'd10)
state<=30;//10
else
state<=29;//9
end

30://10
begin
spi_sck=0;
if(counter2==5'd20)
state<=28;//8
else
state<=30;//10
end

31://11

begin
spi_sck=1;
//data_adc0[kire_14bit]<=spi_miso;
//spi_miso<=data_adc0[kire_14bit];
enable1<=1;
if(counter2==5'd10)
state<=32;//12
else
state<=31;//11
end

32: //12
begin
spi_sck=0;
if(counter2==5'd20)
state<=33;//13
else
state<=32;//12
end

33://13
begin
kire_14bit<=kire_14bit-1'b1;
counter3<=counter3+1'b1;
if(kire_14bit==0)
state<=34;//14
else
state<=31;//11
end

34://14
begin
enable1<=0;
kire_14bit<=4'd13;
spi_sck=1;
if(counter2==5'd10)
state<=35;//15
else
state<=34;//14
end

35://15
begin
spi_sck=0;
if(counter2==5'd20)
state<=36;//16
else
state<=35;//15
end

36://16
begin
counter3<=counter3+1'b1;
if(counter3==6'd18)
state<=37;//17
else
state<=34;//14
end

37://17
begin

spi_sck=1;
enable2<=1;
//spi_miso<=data_adc1[kire_14bit];
if(counter2==5'd10)
state<=38;//18
else
state<=37;//17
end

38://18
begin
spi_sck=0;
if(counter2==5'd20)
state<=39;//19
else
state<=38;//18
end

39://19
begin
kire_14bit<=kire_14bit-1'b1;
counter3<=counter3+1'b1;
if(kire_14bit==0)
state<=40;//20
else
state<=37;//17
end

40://20
begin
enable2<=0;
kire_14bit<=4'd13;
spi_sck=1;
if(counter2==5'd10)
state<=41;//21
else
state<=40;//20
end

41://21
begin
spi_sck=0;
if(counter2==5'd20)
state<=42;//22
else
state<=41;//21
end

42://22
begin
counter3<=counter3+1'b1;
if(counter3==6'd34)
state<=43;//23;
else
state<=40;//20
end

43://23
begin
//ad_conv<=0;
kire_adc<=kire_adc+1'b1;
if(kire_adc==4'd3)
state<=44;//24
else
state<=43;//23
end

44: //24
begin
//ad_conv<=1;
spi_sck=0;
kire_adc<=kire_adc+1'b1;
if(kire_adc==4'd7)
state<=45;//25
else
state<=44;//24
end

45: //25
begin
kire_adc<=0;
counter3<=6'd0;
ad_conv<=0;
state<=6;
end


endcase

end
end

//////////////////program untuk led run dgn slow clock/////////////////////////////
always@(posedge sclk or posedge reset)
begin
if(reset)
led<=0;
else
led<=data_adc2[13:6];

end
/////////////////////////////////////////////////////////////////
always@*
begin

if(reset)
begin
data_adc1<=0;
end

else if((enable1==1) &&(spi_sck==1))
begin

data_adc1[kire_14bit]<=spi_miso;
end

end
/////////////////////////////////////////////////////////////
always@*
begin

if(reset)
begin
data_adc2<=0;
end

else if((enable2==1) &&(spi_sck==1))
begin

data_adc2[kire_14bit]<=spi_miso;
end

end
/////////////////////////////////////////////////////

endmodule