1/f noise of PMOS and NMOS

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hmsheng

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Why it is believed that PMOS devices exhibit less 1/f noise than NMOS transistors?
 

hmsheng said:
Why it is believed that PMOS devices exhibit less 1/f noise than NMOS transistors?
There are two theories behind the physical origins of 1/f (flicker) noise: Hooge's mobility fluctuation theory, and McWhorter's carrier density (or number fluctuation) model. The number fluctuation model is based on the random trapping and release of mobile carriers in traps located at the Si-SiO2 interface of a MOSFET.

In a PMOS device, the mobile carriers (holes) move in a "buried channel" rather than right along the oxide-silicon interface. Since the carriers are distanced from the traps in the gate oxide, the 1/f noise is reduced.

However, reduced 1/f noise is not consistently observed in PMOS vs. NMOS devices on the same process. I have seen plenty of process data sheets which show 1/f noise of the PMOS and NMOS devices to be the same. On one process I recently used, the PMOS devices had worse 1/f noise than the NMOS devices.
 

    hmsheng

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1/f noise is because of the suface state of the silicon-SiO2 surface,the careier such like electrons and holes randomly scattered by the suface states such like dangling bonds.etc. Because the holes transportation occures deeper in the channel compared with electrons,so holes are influenced less by the suface states.and so PMOS has less 1/f noise than NMOS.
 

this isn't a general case , sometimes PMOS is worse (i.e. it is process dependent)
 

i/f noise is inversely proportional to WL. Increase of WL decreases flicker noise. Is there any other techniques to deal with the issue?
How accurate are the simulators regarding the noise in very low frequencies near dc?
 

mitrobge said:
i/f noise is inversely proportional to WL. Increase of WL decreases flicker noise. Is there any other techniques to deal with the issue?
Chopping and auto-zeroing are useful techniques for handling 1/f noise in amplifier circuits (**broken link removed**).

How accurate are the simulators regarding the noise in very low frequencies near dc?
What is your definition of "near DC?" Some people consider 500KHz to be a low frequency, whereas others are focused on the audio band of 20Hz - 20KHz. The simulators are reasonably good, but the real problem is getting the fab to characterize the 1/f noise model parameters properly. Most fabs are too lazy to do it properly, so your simulations give you inaccurate results.
 

For me the band of interest is from dc to 1 Khz for a sigma delta DAC. Do you think flicker noise will be critical for the performance of circuits (switched capacitor architecture for post filtering).
 

hmsheng said:
Why it is believed that PMOS devices exhibit less 1/f noise than NMOS transistors?

The testing result.
But I don't know why.
 

Chopping and auto-zeroing are useful techniques for handling 1/f noise in amplifier circuits (**broken link removed**).

Hi roadbuster,
I can not access the link, could you please give me other link or send it to my email address?
my email: semiartist@yahoo.com, thanks!

BR,
Alex
 


Which process do you use now?
 

but the 1/f noise frequency can be as high as several Mhz or higher.
 

Apart from the physics-based reasons, there is also the fact that pMOS transistors are usually sized larger then nMOS transistors. Since 1/f noise depends on area of the gate, it is less for a pMOS transistor as compared to an nMOS transistor with the same transconductance/current.
 

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