Shady Ahmed
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Can anyone help me please regarding the design of a 1.5 bit current steering DAC as i am not familiar with how it works.
As i understood , i need one cell as this one
As i have 3 levels (represented by Data 1 & Data 0 & Data_1) ... the 2 cases in the image represent Data 1 & Data_1 ... am i right ? or i need 2 cells ? or what as i don't fully understand current steerng DAC concept..
Thanks in advance
As i understood , i need one cell as this one
As i have 3 levels (represented by Data 1 & Data 0 & Data_1) ... the 2 cases in the image represent Data 1 & Data_1 ... am i right ? or i need 2 cells ? or what as i don't fully understand current steerng DAC concept..
Thanks in advance