Assuring stability of SMPS power module?

We are trying to calculate the Feedback loop Bode plots for a 48Vin to 48Vout,3A converter using a PRM48’ SMPS module (as on page 18 of the PRM48’ datasheet below)
As such we wish to calculate the gain & phase margin of this converter….so we can check it will be stable.

The details of the Power stage inside the PRM48’ module are not given in the datasheet, so we need them to provide the small signal power stage and modulator transfer functions in order for us to calculate the “open loop small signal transfer function”.

We can then add in the external output capacitance that we add externally, and get the overall “open loop small signal transfer function”.

However, the PRM48’ datasheet only provides the “Closed Loop output impedance” of the PRM48’ module…..and this is obviously only relevant to the PRM48’ module with its 2uF of internal output capacitance….(not relevant to the value that it actually would be with our extra added in output capacitance).

The below equation (2.13) shows the equation for the “Closed Loop output impedance” of an SMPS..
………………………………………………………
Equation for calculating the Closed Loop output impedance of an SMPS…….

ZOC(s) = Z0(s) / {1+GP(s) _GC(s)} (2.13)
Where:-
Z0(s) = Power stage output impedance.
Gp(s) = Small signal transfer function of modulator and power stage.
Gc(s) = small signal transfer function of the error amplifier.

..Equation 2.13 above is from page 7 of the following…
https://publications.lib.chalmers.se/records/fulltext/202530/202530.pdf
………………………………………………………
In equation 2.13 above, the value “Gp(s).Gc(s)” is obviously the “open loop small signal transfer function”. This is obviously the value that we want. -However, the value of ZOC(s) that the datasheet gives, is the result of doing equation 2.13 on the PRM48’ based SMPS with no external output capacitance, -so it isn’t relevant for us.

….Not only that, but in order to extract the value of Gp(s).Gc(s) from equation 2.13 above, we would need to know “Z0(s)”. However, without knowledge of the actual power stage inside the PRM48’ module, we cannot possibly calculate Z0(s). Therefore, how can we calculate gain and phase margin for our PRM48’ based SMPS?

We dont have the money to buy an AP300 Gain/phase analyser to actually measure it in the lab

PRM48BH480T200B00 datasheet:-
https://www.vicorpower.com/documents/datasheets/PRM48BH480T200B00.pdf

I have never tried this, its just a wild off the wall random thought that has just suddenly occurred to me after my second cup of coffee.

Suppose we have a completely unknown dc power supply "black box" which represents a power source with some unknown and frequency dependant source impedance.

Suppose we feed some variable frequency energy back into it from a power amplifier and use that to measure the ac source impedance of our "black box" at various frequencies.

I could be desperately wrong here, but might any incipient instability show up as an undesirable rise in ac source impedance at specific frequencies where the internal feedback loop fails due to phase margin reduction ??

The same test could be run with a variety of resistive and reactive loads to see if the situation deteriorates.

It would be completely non invasive, and not that complicated.

They provide a small signal model on page 15?

Unless I'm missing something (I didn't follow through and see where they specified all the values), it would be fairly simple to simulate that model in LTSpice and run AC simulations to generate the bode plot. They show examples later on which appear to be a straightforward Type II compensation.

Thanks, but i dont think it can be worked out from page 15.
As you know, all they have to do is give the small signal open loop transfer function….and in this case it would just need a section for the user to include their added external output caps…….then it would be job done…I am not sure why they have not done this.

On a quick look this is what I get modeling page 15 and it seems reasonable. A single pole at ~1khz. It matches their bode diagrams on page 19 and seems straightforward to add your circuit specifics (Cout) and compensation around it. Right?

Thanks, but youve plotted an RC pole reponse.....that cannot be the power stage transfer function of the smps inside that module...no smps power stage small signal transfer function can be boiled down to be that simple.

I suggest you start injecting signals into an active load and monitor V,I for gain phase stability.

You can get a sweep generator from Audacity, and use the audio inputs AC coupled as required to measure the response in time and frequency spectrum, or use scope for unity gain and measure phase margin,



common 2nd order control loops have lead-lag compensation over 1 decade range around unity gain bandwidth so RC//10RC for two series // RC feedback elements in parallel with Dc feedback.

This shows config for Zout, loop gain, and Vctrl sensitivity.

treez said:

Thanks, but youve plotted an RC pole reponse.....that cannot be the power stage transfer function of the smps inside that module...no smps power stage small signal transfer function can be boiled down to be that simple.

Click to expand...

That's not really true. A current mode voltage converter approximates well with first order model.

There are a couple possibilities here. One is that the internal micro closes an internal current loop that they don't tell you about. Second is that their topology/modulation scheme may approximate to exactly their model: a current source (with a limit) feeding a cap. Drawing from experience a phase shifted dual active bridge can approximate to just that. It's all the more plausible that this is an adequate model because it appears the cutoff is quite low, perhaps around 1k. If there is any higher frequency content it's dominated by a lower frequency pole.`

The thing is that as you know you would expect the power stage small sig tran func of even a current mode converter to be the load pole and the esr zero...not just a single pole.

It seems plausible that the ESR zero is high enough for the dominant pole to make it almost irrelevant. You may want to model ESR of your external caps, but this datasheet is clearly suggesting they don't think you need to worry about their ESR.


As an aside, one thing I was slow to come around on when looking at this control stuff is that compensation isn't about stability as much as performance. You can make an LC buck converter stable with a sufficiently low frequency single pole. The reason to use, say, Type II compensation is to raise the gain and push the crossover into higher frequencies and thus improve performance. It's not required for stability.

In this case the bandwidth of the supply as configured may just be sufficiently far enough away from the ESR zero that it doesn't matter. Unless your application demands 50khz+ bandwidth? But why would it?

Looks like I can't edit anymore....I meant "Type III" when I said "Type II" above.