appu1985
Member level 2
verilog error-[ind]
On synthesizing it gives the error as below
Pls let me know wat to do
Code:
module pelement(ii, xi, pi, psi, clk, m1, m2, io, xo, po, psj);
//Parameters Learning Rate of the Neural network
parameter lrate = 1;
//Input ports of the processing element
input [5:0] ii; //Index of the pixel input to the processing element
input [7:0] xi;//Pixel value input to the processing element
input [3:0] pi;//Index of the number of persons whose image is being input
input [7:0] psi;//Partial Sum Input from the previous processing element
input clk;
input m1;//Select Signal for Deciding upon the mode of operation whether Training or Recognition
input m2;//Select Signal for deciding upon in the Training mode if we have to calculate the output or Update the weights
//Output ports of the processing element
output [5:0] io;//Output the index of the pixel
output [7:0] xo;//output of the pixel value
output [3:0] po;//Output of the Person index
output [7:0] psj;//Output the updated Partial sum calculated in this Processing element
//Register Definition
reg [7:0]pso;
reg [7:0]y [9:0];
reg [7:0]yrecog;
reg [7:0] w [4095 : 0];
reg [7:0]psw;
reg [7:0]yrec;
reg [7:0]psj;
reg [5:0] io;//Output the index of the pixel
reg [7:0] xo;//output of the pixel value
reg [3:0] po;//Output of the Person index
//Wires
wire [7:0]g;
wire [7:0]w1;
wire [15:0]d;
wire [15:0]out;
wire [15:0]temp;
wire [15:0]y2;
wire [31:0]temp1;
wire [7:0]regr;
wire [7:0]pj;
always @(clk)begin
io = io;
xo = xo;
po = po;
end
out1 s1(xi,w[ii],psi,pj);
always @ (m1 or m2)
begin : abc1 //This is for Calculatig the output vector.
if(m1 != 0)begin
if(m2 != 0)begin
if(ii >= 4095)begin
y[pi] = psj;
end
end
psj = pj;
io = ii;
xo = xi;
po = pi;
end
end
out2 s2(w[ii],y[pi],xi,psw,g,w1);
always @(m2)begin
if(m1 != 0)begin //This is for updating the weight vector.
if(m2)begin
begin
psw = g;
w[ii] = w1;
io = ii;
xo = xi;
po = pi;
psj = psw;
end
end
end
end
mult m6(xi,w[ii],regr);
add a4(yrec,regr,tempre);
always @(m1)begin
if(ii >= 4095)begin
yrecog = yrec;
end
else
begin
yrec = tempre ;
end
end
endmodule
module out2(w,y,xi,psw,g,w1);
parameter lrate = 0.01;
input [7:0]y ;
input [7:0] xi;
input [7:0] w ;
input [7:0]psw;
wire [15:0]d;
wire [15:0]out;
wire [15:0]temp;
wire [31:0]temp1;
wire [15:0]y2;
reg k;
output [7:0]g;
output [7:0]w1;
initial
begin
assign k = lrate;
end
mult m2(k,y,d);
mult m3(d,xi,out);
add a2(out,w,temp);
mult m4(y,y,y2);
mult m5(y2,w[ii],temp1);
add a3(temp1,psw,g);
subtract s1(temp,temp1,w1);
endmodule
module out1(xi,w,psi,psj);
input [7:0] xi;
input [7:0] w ;
input [7:0] psi;
wire [7:0]t;
output [7:0]psj;
wire [7:0]psj;
mult m1(xi,w,t);
add a1(t,psi,psj);
endmodule
module mult(multiplier, multiplicand, product);
input [7:0] multiplier;
input [7:0] multiplicand;
output [15:0]product;
reg [15:0]product;
integer i;
always @ (multiplier or multiplicand)
begin
product = 0;
for(i=0;i<8;i=i+1)
if(multiplier[i]==1'b1)product = product + (multiplicand<<i);
end
endmodule
module add(a,b,c);
input a;
input b;
output c;
assign c = a + b;
endmodule
module subtract(a, b, c);
input [15:0] a;
input [31:0] b;
output [31:0] c;
assign c = a - b;
endmodule
On synthesizing it gives the error as below
FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.17 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. For more information on this error, please consult the Answers Database or open a WebCase with this project attached at https://www.xilinx.com/support.
Pls let me know wat to do