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Best way to build big LUT

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Tetra

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I want to build a big LUT in VHDL. What is the best way to build it without sacrifizing the VHDL generality (i.e without using technology specific memory)

regards
 

As I understand you correct, you want to write VHDL code with a big LUT in it and you don't want to use special code which is only for e.g. Altera or Xilinx?
 

That is right
 

Good, all you have to do is to declare a big constant array with all the information you want to have as your LUT. The synthesis tool will recognize your code as a ROM. If the array is very big the data will be stored in the system depending space of your FPGA (Altera -> EAB, Xilinx -> Embedded BlockRAM).

by,
cube007
 

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