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problem with instantiating Coregen modules

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Laplace

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Eventhough I instantiate CoreGen generated cores in my top level HDL code (or schematic), When I looked at the post-synthesis RTL level design schematic in ECS, I see that input and out data ports are not connected.

Any sugesstions?


Thanks,
Laplace
 

I have found the same problem on my design and in particular on the bus signals. No problem, it is only a graphical error but the design , and then the synthesis, is ok!
 

thanks

But, i think this is a crucial error here and to be solved urgently. Is there any service pack in order to correct this error?
 

Re: thanks

Laplace said:
But, i think this is a crucial error here and to be solved urgently. Is there any service pack in order to correct this error?
Click to expand...

unfortunately it isn't the only problem and I think that it is the minus important.
More severe are problems during the mapping ( inconsistency of the design).
the use of the hierarchical design flow is very unstable and the result is unforeseeable.
I'm very very dissatisfied.
 

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