Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to design this asynchronous counter 0-2-4-3-7-6?

Status
Not open for further replies.

student2005

Member level 3
Joined
Sep 23, 2005
Messages
57
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,288
Activity points
1,793
asynchronous counter design

I refer to reference books like Tocci, Kleitz, and Floyd, but could not find an example that shows how to design an asynchronous counter.

I wish to design an asynchronous counter that repeat the following sequence:
0 -> 2 -> 4 -> 3 -> 7 -> 6 -> 0...

Positive-triggered JK FF should be used to implement the counter.

Please advise.

Many thanks.
 

With a synchronous counter is rather easy and i can help you eith that, but with asynchronous i don't know. I guess it will be more complex.
 

ckck20 said:
With a synchronous counter is rather easy and i can help you eith that, but with asynchronous i don't know. I guess it will be more complex.
I know the procedure to design a synchronous counter. Not sure we can apply the same design produres for the design of asynchronous counter or not. I could not find an example in the references book mentioned in my first post. Also, I could not find any example using Google... It's weird. Therefore, any help is very appreciated.

Thank you in advance.
 

well you are going to use 3 ff (jk) (A,B,C)

Ja=B,Ka=~C

Jb=1 (Vdd) ,Kb=A+~C

Jc=A*(~B), Kc=A


Try it and let me know
 

fidjouss100 said:
well you are going to use 3 ff (jk) (A,B,C)

Ja=B,Ka=~C

Jb=1 (Vdd) ,Kb=A+~C

Jc=A*(~B), Kc=A
I have not tried yet. BTW, how did you come to these equations? Pls advise. Many thanks.
 

From a first look, i think those equations are for a syncronous counter, not an asynchronous. I don't have time right now to look into it and say for sure.
But if they are indeed for asynchronous i'd like to know too how we concluded those equations.
 

An asynchronous counter that uses edge-triggered flops? Does that make sense to anyone? It sounds like a contradiction.
 

echo47 said:
An asynchronous counter that uses edge-triggered flops? Does that make sense to anyone? It sounds like a contradiction.

I think that An asynchronous counter Can use edge-trigerred FF.

It 's called Asynchronous because there is no one clock driving all it's FF,
The first FF is driven by the clock, the second one takes it's clock from the output of the first one, the third takes it's clock from the output of the second, and so on..

So there is no Contradiction between using edge-Triggered FF in implementing Asynchronous Counter
 

I think you guys are right. that was for synchronous counter.
I will work on the asychronous part and try to post it.
 

As another way, you can use HDL based design methodology!
 

Johnson said:
As another way, you can use HDL based design methodology!
I think this is an easier way. Unfortunately I have never learned HDL before. So, any hints? Thanks.
 

The equations given above are correct. Ive check it.

the procedure are roughly derscribe as:
1.) make state diagram
2.)make state table
3.) Set JK inputs
4.) Make K map for JK inputs
5.)you get your equation
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top