E
expertengr
Guest
Hello,
I am wondering about reliable technique to solve metastability in VHDL. One way is double sample of data_ready signal using two FF in series. Here is an example.
Are there other methods to solve metastability ?
I am wondering about reliable technique to solve metastability in VHDL. One way is double sample of data_ready signal using two FF in series. Here is an example.
Code:
if rising_edge(clk) then
-- double sample to avoid metastability
ready_r <= data_ready;
ready_rr <= ready_r;
-- detect the rising edge of ready signal
if ready_r = '1' and ready_rr = '0' then
end if;
Are there other methods to solve metastability ?
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