kocchop
Newbie level 3
I am using the following coding pattern to latch a data:
To latch a data in a particular register, I have to set a latch_enable signal high. And I am enabling this latch_enable signal at clock cycle n because I want the data to be latched at clock cycle n+1. And at clock cycle n+1, I am disabling the latch_enable signal under the assumption that the data is already latched at the posedge clk.
But the thing is, my data is being latched at same posedge clk at which the latch_enable (responsible for the data storage) signal is being driven low.
So, I think I am facing a kind of race condition in my RTL design. Under the normal conditions, there may be some parasitic delay added while driving the latch_enable signal low. But would that be enough?
I have seen the above mentioned practice in some other RTL codes. That's why, I just want to clarify if my thoughts are ok or not.
And if really such race condition occurs, then what practice should I follow to avert this problem?
Thanks in advance.
To latch a data in a particular register, I have to set a latch_enable signal high. And I am enabling this latch_enable signal at clock cycle n because I want the data to be latched at clock cycle n+1. And at clock cycle n+1, I am disabling the latch_enable signal under the assumption that the data is already latched at the posedge clk.
But the thing is, my data is being latched at same posedge clk at which the latch_enable (responsible for the data storage) signal is being driven low.
So, I think I am facing a kind of race condition in my RTL design. Under the normal conditions, there may be some parasitic delay added while driving the latch_enable signal low. But would that be enough?
I have seen the above mentioned practice in some other RTL codes. That's why, I just want to clarify if my thoughts are ok or not.
And if really such race condition occurs, then what practice should I follow to avert this problem?
Thanks in advance.