dayana42200
Junior Member level 3
Hi everyone.
This is my power report from Design Compiler.
My questions are
1. Which is the total static power?
2. From what I know, total power is the summation of static power and dynamic power. Do cell leakage power included in the total power calculation?
3. Can anyone kindly explain to me the difference between FPGA and ASIC and how does the different affects the total power calculation?
This is my power report from Design Compiler.
Code:
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Report : power
-analysis_effort low
Design : ProcessingElement
Version: J-2014.09-SP2
Date : Mon Feb 26 08:44:25 2018
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Library(s) Used:
cb13fs120_tsmc_max (File: /home/dayana/Desktop/chip_design/ref/db/sc_max.db)
Operating Conditions: cb13fs120_tsmc_max Library: cb13fs120_tsmc_max
Wire Load Model Mode: enclosed
Design Wire Load Model Library
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ProcessingElement 8000 cb13fs120_tsmc_max
Global Operating Voltage = 1.08
Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 1.000000pf
Time Units = 1ns
Dynamic Power Units = 1mW (derived from V,C,T units)
Leakage Power Units = 1pW
Cell Internal Power = 37.7363 uW (64%)
Net Switching Power = 20.8824 uW (36%)
---------
Total Dynamic Power = 58.6186 uW (100%)
Cell Leakage Power = 7.4366 uW
Internal Switching Leakage Total
Power Group Power Power Power Power ( % ) Attrs
--------------------------------------------------------------------------------------------------
io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
memory 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
clock_network 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
register 8.4086e-03 2.2963e-03 2.4861e+06 1.3191e-02 ( 19.97%)
sequential 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
combinational 2.9328e-02 1.8586e-02 4.9505e+06 5.2864e-02 ( 80.03%)
--------------------------------------------------------------------------------------------------
Total 3.7736e-02 mW 2.0882e-02 mW 7.4366e+06 pW 6.6055e-02 mW
1. Which is the total static power?
2. From what I know, total power is the summation of static power and dynamic power. Do cell leakage power included in the total power calculation?
3. Can anyone kindly explain to me the difference between FPGA and ASIC and how does the different affects the total power calculation?