mjuneja
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Code:
process(rst,clk,x,z)
begin
if ((rst = '0') or (z = '1')) then
y <= '0';
elsif(rising_edge(clk)) then
if(x = '1') then
y <= '1';
end if;
end if;
end process;
In the above shared VHDL code for defining a register, 'rst' is the global reset for the whole circuit and 'clk' is the global clock.
My query is regarding usage of gated reset for defining register that whether
1. It is a good practice to use gated reset as I have shown in the code ?
2. What are the implications of using gated resets (if any) ?
please share some insights over it