Nyom
Newbie level 3
I am getting error in verilog code while compiling using Quartus II as under
Line 313 is
code for the test bench module is
Any suggestions for rectifying the same. I am generating a 0.1 second delay..
Error (10119): Verilog HDL Loop Statement error at DE1_SOC_golden_top.v(313): loop with non-constant loop condition must terminate within 250 iterations
Line 313 is
Code:
#50 clock = ~clock;
code for the test bench module is
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 // Outputs wire [3:0] d0; wire [3:0] d1; wire [3:0] d2; // Instantiate the Unit Under Test (UUT) stopwatch uut ( .clock(clock), .reset(reset), .start(start), .d0(d0), .d1(d1), .d2(d2) ); initial begin clock = 0; forever #50 clock = ~clock; end initial begin // Initialize Inputs reset = 0; start = 0; // Wait 100 ns for global reset to finish #100; reset = 1; #100; reset = 0; #100; start = 1; // Add stimulus here end
Any suggestions for rectifying the same. I am generating a 0.1 second delay..
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