hcu
Advanced Member level 4
Hello,
how can i write the "second always block" to look as a "first always block". I tried with a "for loop" but the simulator returns error.
my intent is to reduce the no.of lines.
Here a sample code:
suggest me the way, In my real scenario .i have to do it for about 100's of lines at various locations.
how can i write the "second always block" to look as a "first always block". I tried with a "for loop" but the simulator returns error.
my intent is to reduce the no.of lines.
Here a sample code:
Code:
module example(
input clk,
input rst,
input vld,
input [15:0] data_in,
output reg data_out
);
reg [3:0] delta [3:0];
reg [3:0] beta [3:0];
integer i;
//first block
always@(posedge clk)
if(vld)
begin
delta[0] <= data_in[3:0];
delta[1] <= data_in[7:4];
delta[2] <= data_in[11:8];
delta[3] <= data_in[15:12];
end
//second block
always@(posedge clk)
if(vld)
begin
for(i=0;i<=3;i=i+1) begin
beta[i] <= data_in[(4*(i+1))-1:(4*i)] ;
end
end
endmodule
suggest me the way, In my real scenario .i have to do it for about 100's of lines at various locations.
Last edited: