hareeshP
Member level 3
Hi all,
I'm using Altera SignalTap for monitoring the pins of fpga. We have two clock one for fpga which is 20MHz and another one is a 50MHz clock(we call it ifc clock) which coming from processor. Some registers are initialized based on the rising_edge of ifc clock and the register transmission happens. I have configured signaltap for monitoring the register values, and i have used the ifc clock as sampling clock. When run the analysis it showing like "waiting for clock".
Could anyone help me?
Thanks and regards
Hareesh.
I'm using Altera SignalTap for monitoring the pins of fpga. We have two clock one for fpga which is 20MHz and another one is a 50MHz clock(we call it ifc clock) which coming from processor. Some registers are initialized based on the rising_edge of ifc clock and the register transmission happens. I have configured signaltap for monitoring the register values, and i have used the ifc clock as sampling clock. When run the analysis it showing like "waiting for clock".
Could anyone help me?
Thanks and regards
Hareesh.