Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

if (max[M:0] > value) in verilog...where M is input...Alternative

Status
Not open for further replies.
T

tayyab786

Junior Member level 3
Joined
Mar 11, 2017
Messages
28
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
224
get error on this statement if (max[M:0] > value) where M is input... i know we cannot declare a value in an array that can change at run time ....any alternative for this statement
 

The basic way I can think of would be to generate a lookup table of 1, 3, 7, F, 1F, 3F, etc... Then you can do (max&mask[M]) > value.

There are a variety of ways this can be done. I'd actually like to see if anyone has a good way to do this in Verilog. I've done stuff like this in the past, but compared to VHDL it just feels like a hack. In VHDL you can declare the array type, write a function, and use it to initialize a constant.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top