sanjaysharmaiitk
Member level 1
I compared LAYOUT vs CLD netlist of UART design by RTL code and gds exported into Virtuoso.
There are no error but following warning is coming during PEX in calibre .
"The ground net "VSS/VSSO" defined in PEX NETLIST statement is not a valid GND net in the design."
what is the cause of this warning ,How to remove this warning.
In LAYOUT VSS,VSSO VDD ,VDDO dc supply are used for PADs and VDD ,VSS are common to both for PADs and Chip.
VSS, VDD are supplied to both Core-Ring and to PAD-ring by PADs defined in PDK for supply to both PAD-RING and CORE-RING.
scl pdk is used for design.
There are no error but following warning is coming during PEX in calibre .
"The ground net "VSS/VSSO" defined in PEX NETLIST statement is not a valid GND net in the design."
what is the cause of this warning ,How to remove this warning.
In LAYOUT VSS,VSSO VDD ,VDDO dc supply are used for PADs and VDD ,VSS are common to both for PADs and Chip.
VSS, VDD are supplied to both Core-Ring and to PAD-ring by PADs defined in PDK for supply to both PAD-RING and CORE-RING.
scl pdk is used for design.