josephine1234
Junior Member level 1
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 module fix(x,z,x1 ); input signed [4:0]x; output z; output signed[14:0]x1; localparam signed [11:0] y = 12'b100000000000; reg [14:0]z; always @* begin z=x*y; end // selecting msb reg z1; always @* begin z1=x[4]; end // to check if number is positive or negative reg [14:0]x1; always @( z or z1) begin if (z1 == 1) x1 = ~z; else x1 = z; end endmodule
this is the code to get one input .. can anyone help me in iterating this code so as to get 32 inputs... many thanks in advance....
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