Amr_Rashed
Newbie level 4
Hello,
I have designed a Finite State Machine in VHDL and I simulated the code using Modelsim and testbench, and the code works Great. I am using an open source tool called Alliance to make the synthesis and pnr etc and generate the GSD2 file by the end of this project. when I try to run the synthesis tool (SYF) this errors pop up (check the attached photo) and I don't know where do the errors come from.
I tried other FSM code written in VHDL and it worked well, so SYF works fine.
(The rest of errors come from and value assertion to the NS( next_state) signal).
Thanks in Advance.
this is the Error message
This is The Entity and architecture declaration
I have designed a Finite State Machine in VHDL and I simulated the code using Modelsim and testbench, and the code works Great. I am using an open source tool called Alliance to make the synthesis and pnr etc and generate the GSD2 file by the end of this project. when I try to run the synthesis tool (SYF) this errors pop up (check the attached photo) and I don't know where do the errors come from.
I tried other FSM code written in VHDL and it worked well, so SYF works fine.
(The rest of errors come from and value assertion to the NS( next_state) signal).
Thanks in Advance.
this is the Error message
This is The Entity and architecture declaration