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Multiplexer in VHDL with a 2D array and for loop

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moonshine8995

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Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
use work.CONV_PACK_Top.all;
entity mux_top is
    Port ( sel : in  STD_LOGIC_VECTOR (31 downto 0);
           mux_in   : in  T_2D;
           mux_out   : out STD_LOGIC_VECTOR (31 downto 0));
end mux_top;

architecture Behavioral of mux_top is
begin
process(sel)
begin
mux_out <= mux_in(to_integer(unsigned(sel)));
--output_4a <= to_integer(unsigned(sel));
end process;
end Behavioral;
i cant write a loop in the architecture to work correctly
i got error for line
Code: 
process(sel) and mux_out <= mux_in(to_integer(unsigned(sel)));
in simulation.
the error is Fatal error in Process line__17.
mux_in is a 2D array which as 30 in put than all of them are 32bit.
i tried with for generate
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
use work.CONV_PACK_Top.all;
entity mux_top is
    Port ( sel : in  STD_LOGIC_VECTOR (31 downto 0);
           mux_in   : in  T_2D;
           mux_out   : out STD_LOGIC_VECTOR (31 downto 0));
end mux_top;

architecture Behavioral of mux_top is
begin
GEN: for i in 0 to 29 generate
      	   mux_out <= mux_in(i);
     end generate;
     mux_out <= mux_in(sel);
end Behavioral;
in didn't work either.
thanks for helping me.
 

your code expects T_2D to have over 2 Billion entries, because sel is 32 bits wide. It will wrap around and be truncated if sel the MSB of sel is set. Is this what you meant?
Maybe you need to make the width of sel smaller?
 
you are right thank you.
this ia my test bench
entity mux_tb is

end mux_tb;

architecture Behavioral of mux_tb is
signal sel : STD_LOGIC_VECTOR (15 downto 0);
signal mux_in : T_2D;
signal mux_out : STD_LOGIC_VECTOR (31 downto 0);
component mux_868to1_top is
Port ( sel : in STD_LOGIC_VECTOR (15 downto 0);
mux_in : in T_2D;
mux_out : out STD_LOGIC_VECTOR (31 downto 0));
end component;
begin
dut: mux_868to1_top port map
(sel => sel,
mux_in => mux_in,
mux_out => mux_out

);
sel <= X"0001";
end Behavioral;
Click to expand...
where is my problem that i cant see the output?
 

Possible answers could be:
You have an uninitialised signal somewhere
Something is unconnected
you forgot to add a signal to the wave viewer
you didnt start a simulation
you didnt load the simulator
you didnt compile the correct code
you are wearing dark glasses
your monitor is turned off
you need to increase the monitor's brightness/contrast
you have a black and white monitor and the wave is in colour
You are blind
you have no eyes

All possible answers to your problem. Please rephrase the question to be more specific.

- - - Updated - - -

But it is likely that you didnt assign anything to mux_in
 
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