rahdirs
Advanced Member level 1
Suppose, I have a vector:
I want to OR the even bits & odd bits seperately, as in x_even = x[0] | x[2] | x[4] | ...... x[126] & similarly for the odd bits. I tried the following but it's pointing a syntax error at |=
Regards,
rahdirs
Code Verilog - [expand] 1 logic [127:0] x; // one hot
I want to OR the even bits & odd bits seperately, as in x_even = x[0] | x[2] | x[4] | ...... x[126] & similarly for the odd bits. I tried the following but it's pointing a syntax error at |=
Code Verilog - [expand] 1 2 3 4 5 6 generate for (i=0;i<64;i++) begin x_even |= x[2*i]; x_odd |= x[2*i+1]; end endgenerate
Regards,
rahdirs