matin-kh
Member level 3
hi every one,
I have a spartan 6(XC6SLX150) which it's input clock is a differential pair and it's value is 12.8Mhz, I understood which I couldn't use pll_base because it's minimum input frequency should be 19MHz. If I want to use Pll_base can I produce a frequency higher than 12.8 MHz with CMD_CLKGEN and define it's output clock to a signal in top module and define this signal as the input of another cmt and use this as the input of the base_pll? I mean it doesn't matter that the input of the pll_base does not enter from gclk and it's a signal which this signal is the output of the DCM_CLKGEN?please if it is not a correct path tell me the correct path
Regards
Matin
I have a spartan 6(XC6SLX150) which it's input clock is a differential pair and it's value is 12.8Mhz, I understood which I couldn't use pll_base because it's minimum input frequency should be 19MHz. If I want to use Pll_base can I produce a frequency higher than 12.8 MHz with CMD_CLKGEN and define it's output clock to a signal in top module and define this signal as the input of another cmt and use this as the input of the base_pll? I mean it doesn't matter that the input of the pll_base does not enter from gclk and it's a signal which this signal is the output of the DCM_CLKGEN?please if it is not a correct path tell me the correct path
Regards
Matin