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assign class = (svm[49]) ? 1b'1 : 1b'0;
Code VHDL - [expand] 1 2 3 4 -- a mux/switch x <= a when b else c; -- constant assign y <= consant
Code Verilog - [expand] 1 2 3 4 // mux or switch assign x = b ? a : c; // constant assignment assign y = somevalue;
Code Verilog - [expand] 1 2 3 4 always @ * begin if b==1 x = a; else x=c; //Verilog uses begin and end as c language { } end