UltraGreen
Junior Member level 3
Xilinx fpga ultrascale vivado 2016.2
The design is utilizing 80% of the device and earlier it used to route with =synthesis stratagy - flow alternate routability & congestoion spread logic high for implementation
now I had to create a small 4 bit counter in the top module and the design is not routing.
I tried multiple times and the result is same ( although the set up , hold and no. of overlap nodes does change with every run. )
I cannot reduce the logic anymore, please suggest some way to get a clean bitfile.
Thanks
The design is utilizing 80% of the device and earlier it used to route with =synthesis stratagy - flow alternate routability & congestoion spread logic high for implementation
now I had to create a small 4 bit counter in the top module and the design is not routing.
I tried multiple times and the result is same ( although the set up , hold and no. of overlap nodes does change with every run. )
I cannot reduce the logic anymore, please suggest some way to get a clean bitfile.
Thanks