Janoy66
Newbie
Hi there,
I am new to this forum as well as i am new to VHDL. Teacher gave as a test to do at home and i have struggles with one of the test.
We got a code and our task is to analyze it and write down the purpose of the Device. We also have to explain the the purpose of parameter s and out_sig, in_sig, mode, clk ports.
What i see is that we got a D-trigger, but what is the purpose of it in this specific program - i dont understand.
Obviously, the clk port is for clock, is there any deeper explanation for that?
In_sig acts like and input signal and out_sig is for output signal, which is controlled by the trigger, right?
The code is following:
I am new to this forum as well as i am new to VHDL. Teacher gave as a test to do at home and i have struggles with one of the test.
We got a code and our task is to analyze it and write down the purpose of the Device. We also have to explain the the purpose of parameter s and out_sig, in_sig, mode, clk ports.
What i see is that we got a D-trigger, but what is the purpose of it in this specific program - i dont understand.
Obviously, the clk port is for clock, is there any deeper explanation for that?
In_sig acts like and input signal and out_sig is for output signal, which is controlled by the trigger, right?
The code is following:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 entity Device is generic ( s : integer); port ( out_sig : out std_logic; in_sig : in std_logic_vector(s-1 downto 0); mode : in std_logic; clk : in std_logic ); end Device; architecture Program of Device is component DFF is -- DFF is a synchronious D-trigger port ( Q : out std_logic; D : in std_logic; Clk : in std_logic ); end component; signal d, q, in_value : std_logic_vector(s-1 downto 0):= (others => '0'); signal i : integer := 0; begin in_value <= in_sig; out_sig <= q(0); g1: for i in 0 to s-1 generate begin DFF_inst : DFF port map ( CKJ => clk, D => d(i), Q => q(i) ); end generate g1; process (mode, in_sig, q) begin if mode= '0' then d<= in_sig; else d <= '0'& q(s-1 downto 1); end if; end process; end Program
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