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how to decide , how many BARS are needed while configuring axi_pcie core in vivado??

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anilineda

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I am so much confused while configuring the "axi memory mapped to PCIe" core in vivado design suite.
how to decide the no of bars in the tab: pcie: bars and also in AXI: BARS. please look in the figure Picture2.png

please be more specific, Dumb is sitting here

if possible give some notes, other than the xilinx pdf.
 

BARS == Base address registers...

That would indicate that it's the first address for a memory block on the device that needs to be memory mapped on the host.

e.g. Memory mapped: control registers, input data buffer, and output data buffer could all reside at different base addresses.
 

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