MIG doesn't seem to read (or write).

This is for a school project and I've been struggling for months now, I had to learn this all from scratch with no help. So I'm asking for some help now.
The board I'm using is a Trenz TE0710, it has a Artix 7 35t.
I've included my code, if anyone wants to help a troubled person.

I've made sure that init_calib_complete is asserted and app_rdy is asserted through sending the signal to a port and checking it.
So I believe the memory gets initialized, but when I'm sending a signal through my user interface to write, and then read. Nothing happens.
I checked app_rd_data_valid by also sending it through to a top level port, and it never gets asserted after the doing a read.

I don't understand how people are able to simulate their user designs.
I've tried to simulate without the model, because I have no idea how to include it in Vivado simulator.
App_rdy never goes high and although the MIG finishes initializing, all the DDR stuff does nothing.

Thanks for your time.

epicestperson said:

I don't understand how people are able to simulate their user designs.
I've tried to simulate without the model, because I have no idea how to include it in Vivado simulator.
App_rdy never goes high and although the MIG finishes initializing, all the DDR stuff does nothing.

Thanks for your time.

Click to expand...

You go to Micron's web site, find a compatible DDR part and download the verilog/VHDL simulation model. Not sure why that is a problem. Once you have that you instantiate it in the testbench and run the simulation. Nothing happens because you have to have a DDR model to run the simulation, it requires the DDR RAM to exist in the testbench to read and write to perform calibration.

Is it you don't have a testbench? don't know how to instantiate? don't know know how to compile/add files for the simulation?

It's obvious you don't know how to script the simulation yourself, relying on the GUI to do it is useless for understanding how to do stuff, IMO. In a Vivado Tcl shell use the following commands:

use xvlog/xvhdl command to compile each file of your design
xvlog <module_file_name>.v
xvhdl <entity_file_name>.vhd

for a verilog simulation (_ver: not all libraries are necessary only the ones you need)
xelab -debug typical -timescale 1ns/1ps -L work -L unisims_ver -L unimacro_ver -L xilinxcorelib_ver -L secureip <module_file_name>

run the simulation in GUI mode, without the -gui you'll run in command line mode
xsim -gui <module_file_name>

If you absolutely must use the GUI.
Add the testbench and the DDR model and any other models you might have to the source code by adding with simulation only selected uncheck the for synthesis option.

I don't understand how people are able to simulate their user designs.
I've tried to simulate without the model, because I have no idea how to include it in Vivado simulator.

Click to expand...

The MIG for DDR3 is a complex IP.
I would first suggest you to 1st successfully simulate the sim_tb_top that is automatically generated by Vivado for the DDR3 that is available on your Trenz TE0710 board, if you have not done this.

If you have been using the GUI for the MIG generation, the simulation model for the DDR3 will automatically generated by Vivado (one cannot miss the step given below).


Only after you have understood how the interface signals works, should you proceed on replacing the Xilinx *_traffic_gen_top with your own R/W controller.

However if you are not sure of how to simulate a hierarchical design inside a test-bench ads-ee's reply will help you.