vGoodtimes
Advanced Member level 4
I was brushing up on SystemVerilog and decided to try porting some of my old VHDL packages, just to see how different they would be. But I quickly hit an interesting (to me) problem with functions. Here is an example of what I mean:
I was wondering if SystemVerilog had some equivalent structure. Mainly that the size of inputs/outputs/intermediates could be something that was parametized in some way.
It seems that, if the functions were declared inside a module, things might be ok as long as the function isn't called with more than one type of args. But can this be relaxed in a nice way or not?
For example, you can do whatever you want if you use the pre-processor, or have a code generator tool. But that isn't my preferred solution.
It also seems that a module would work in some cases, but removes the function syntax.
Interfaces as arguements might solve the issues with the input, maybe. I'm still looking into what the tools actually allow. I'm not even certain you can construct a new interface as an intermediate term at the moment.
Having the function be a member function of an interface might work as well.
Any comments/experience on pro's/con's of these approaches, or on others you might know.
(In this example, a large vector is created as a constant. This will later be used in another function. The tools can optimize the result into optimal logic fairly easily. It isn't an insane software approach or anything like that, just a way to generate the constants inside the tool.)
Code:
-- I didn't double check the logic in the function, doing this from memory.
function makeMatrix(taps : std_logic_vector; N : natural) return std_logic_vector is
constant R : natural := taps'length;
variable state : std_logic_vector(R-1 downto 0);
variable op : std_logic_vector(R*N-1 downto 0);
begin
state := taps;
for i in 0 to R-1 loop
op(N*i+R-1 downto N*i) := state;
if state(0) = '1' then
state := ('0' & state(C-1 downto 1)) xor taps;
else
state := '0' & state(C-1 downto 1);
end if;
end loop;
return op;
end function;
I was wondering if SystemVerilog had some equivalent structure. Mainly that the size of inputs/outputs/intermediates could be something that was parametized in some way.
It seems that, if the functions were declared inside a module, things might be ok as long as the function isn't called with more than one type of args. But can this be relaxed in a nice way or not?
For example, you can do whatever you want if you use the pre-processor, or have a code generator tool. But that isn't my preferred solution.
It also seems that a module would work in some cases, but removes the function syntax.
Interfaces as arguements might solve the issues with the input, maybe. I'm still looking into what the tools actually allow. I'm not even certain you can construct a new interface as an intermediate term at the moment.
Having the function be a member function of an interface might work as well.
Any comments/experience on pro's/con's of these approaches, or on others you might know.
(In this example, a large vector is created as a constant. This will later be used in another function. The tools can optimize the result into optimal logic fairly easily. It isn't an insane software approach or anything like that, just a way to generate the constants inside the tool.)