Is it safe to use 2 FIFOs

shaiko · Mar 16, 2016

Hello,

The following question originates from a debate I have with a fellow colleague:

We have 2 correlated vectors:
1. A (data vector).
2. B (control vector for A).

We need to transfer both vectors between clock domain X to clock domain Y.

Do you think it would be safe to use 2 separate asynchronous FIFOs (one for each vector)?

TrickyDicky · Mar 16, 2016

Yes. You know when data is available in both, so will always be aligned.

shaiko · Mar 16, 2016

Yes. You know when data is available in both, so will always be aligned.

Suppose both FIFOs are empty and a write operation takes place - to both on the same edge of the X clock domain.
Are you saying it's absolutely guaranteed that the empty flags of both FIFO will de-assert exactly at the same edge of clock domain Y ?

I think there's going to be a certain degree of uncertainty (due to synchronization of 2 different grey counters) - causing the empty flags of both FIFOs to sometimes de-assert on different edges of the Y clock domain.

FvM · Mar 16, 2016

There's an exact 1:1 relation of data points streamed in and out, although no necessarily at the same clock edge for both multiple FIFOs. So everything can be put down to the question if you are handling the handshake signals of both FIFOs correctly.

TrickyDicky · Mar 16, 2016

the logic is pretty straight forward:

both_fifo_rden <= not fifo_data_empty and not fifo_ctrl_empty;

If both fifos have data, then you know it's safe to read from both fifos.

shaiko · Mar 16, 2016

FvM,

So everything can be put down to the question if you are handling the handshake signals of both FIFOs correctly.

By "handshake signals" you mean by what TrickyDicky wrote:

Code:

both_fifo_rden <= not fifo_data_empty and not fifo_ctrl_empty;

?

ads-ee · Mar 16, 2016

shaiko said:
FvM,

By "handshake signals" you mean by what TrickyDicky wrote:

Code:

both_fifo_rden <= not fifo_data_empty and not fifo_ctrl_empty;

?

Well there is also full. If the FIFO goes full you can no longer guarantee alignment. I can also see issues if there are no gaps in writing to the FIFOs. As it will be very hard to assure alignment when restarting. Unless there is some method of ensuring that any FIFO resets are done while no data is being written.

shaiko · Mar 16, 2016

Well there is also full.

Correct - how would you take care of that?

I don't think this would work...

Code:

both_fifo_wren <= not fifo_data_full and not fifo_ctrl_full;

TrickyDicky · Mar 16, 2016

it would work if you know the inputs could never get lost. But it does require that you have backpressure in your system. Without it then all bets are off.

shaiko · Mar 16, 2016

ads-ee,

As it will be very hard to assure alignment when restarting

What do you mean when you say "restarting" ? Why would you want to restart the FIFOs pointers?

ads-ee · Mar 16, 2016

If you overflow you lose any knowledge of alignment, so you would have to reset the FIFO. If you guarantee by design that it can never overflow then only the starting alignment has to be dealt with (i.e. if the writes are continuous you need to guarantee when you enable that there is nothing in the FIFO before the first aligned writes to both FIFOs occur).

shaiko · Mar 16, 2016

If you guarantee by design that it can never overflow then only the starting alignment has to be dealt with

What do you mean by "starting alignment" ?

ads-ee · Mar 16, 2016

your two correlated data streams, must start at the same correlated position. If the write logic doesn't guarantee that correlated data for both streams get written (i.e. a reset allows one to write and stops the other write) then you'll be forever out of alignment.

a b
0 0 <= in reset
0 0 <= reset released but due to re-synchronization...
0 b1 <= a still sees reset, b doesn't
a2 b2 <= first read will see a2 and b1 data due to the reset delaying the write of the first a value.

std_match · Mar 16, 2016

shaiko said:
What do you mean by "starting alignment" ?

You must always put the same number of elements in both FIFO's, so the simplest "starting alignment" is just to make sure that both FIFO's are empty when you begin ...

If the FIFO's are independent, the data may arrive in domain Y in different cycles even if you write them in the same cycle in domain X. The probability is low, but it can happen.
The simplest solution is to OR the empty signals together in the Y domain, if one FIFO is empty, treat both as empty.

If you allow the FIFO's to get full you must also OR the full signals in the X domain. If one FIFO is full, treat both as full (= block writes).

vGoodtimes · Mar 17, 2016

In this post the answer isn't really isn't interesting -- it describes how to take two fifos and combine them into a single fifo. For example, simply creating a new vector that is data+control and using a wider fifo -- something easy to do with existing core generators.

Xilinx also has this "Fifos in parallel" in their manuals, if you need a picture.

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