Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Will "set_max/min_delay" command guide fitter to meet timing in TimeQuest?

Status
Not open for further replies.
N

nervecell_23

Member level 1
Joined
Apr 26, 2013
Messages
38
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,565
I'm new to TimeQuest and have some confusion here:

When I use "set_max/min_delay" command for a particular path in SDC file, is it only used for analyzing the timing eg. simply telling me if that particular path has timing violation based on the specified value, or is the command used to guide the fitting so that the specified value can be met?

If the latter is true, is it possible to constrain a particular clock path/data path ?

Thanks!
 

Re: Will "set_max/min_delay" command guide fitter to meet timing in TimeQuest?

Unless you only specify it for timing analysis, it will also apply to the fitter. Ive seen these type of constraints to make the fitter prioritise specific paths, with over constraints applied to the fitter only to ensure a design meets timing.

Set max delay can be applied like any other constraint ie to a bunch of regs or a particular path. They are only applied for reg-reg paths, not clocks.
 

Re: Will "set_max/min_delay" command guide fitter to meet timing in TimeQuest?

TrickyDicky,
Correct me if I'm wrong - but I think the set_max_delay / set_min_delay are more suitable for constraining I/Os connected to asynchronous logic.

Why would you bother using these commands inside your FPGA if you're working synchronously?
I mean, the tool is well aware of the frequency (create_clock...) - so let it do the job for you.
 

Re: Will "set_max/min_delay" command guide fitter to meet timing in TimeQuest?

shaiko said:
TrickyDicky,
Correct me if I'm wrong - but I think the set_max_delay / set_min_delay are more suitable for constraining I/Os connected to asynchronous logic.

Why would you bother using these commands inside your FPGA if you're working synchronously?
I mean, the tool is well aware of the frequency (create_clock...) - so let it do the job for you.
Click to expand...

Yes that is true, but in the case of synchronization registers I normally add a set_max_delay constraint to ensure that the length of the net associated with the first FF input isn't unconstrained with a set_false_path, instead I use a somewhat arbitrary value of 2x the clock period as a maximum delay for that net.

In the other case of I/O I normally have set_input_delay/output_delay constraints. Any I/O that require a set_max/min_delay constraint are typically just pass through of some sort, or a reset circuit (which are usually the only asynchronous inputs I use). Otherwise every pin ends up at some register be it a synchronous input or going to a synchronizer.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Re: Will "set_max/min_delay" command guide fitter to meet timing in TimeQuest?

shaiko said:
Why would you bother using these commands inside your FPGA if you're working synchronously?
I mean, the tool is well aware of the frequency (create_clock...) - so let it do the job for you.
Click to expand...

But if the design is struggling or fails on one path it tends to give up all over. Overconstraining also makes it prioritise that net, whereas with a general fit it may not have a high priority which causes it to fail regularly.

Using max delays like this should usually be a last resort when you have exhausted standard timing analysis, you have repipelined the code and you've layed down some area constraints.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top