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That is not "clock gating". e.g. Xilinx has BUFGCTRL, BUFGMUX, BUFGMUX_1, and BUFGMUX_CTRL primitives for clock multiplexing. I suppose if you are a masochistic you can "gate" the clock with a LUT feeding the clock input or a LUT feeding a BUFG and try to find a way to constrain the design properly.
Of course sun_ray is probably confusing ASICs with FPGAs and posted this in the wrong section.
That is not "clock gating". e.g. Xilinx has BUFGCTRL, BUFGMUX, BUFGMUX_1, and BUFGMUX_CTRL primitives for clock multiplexing. I suppose if you are a masochistic you can "gate" the clock with a LUT feeding the clock input or a LUT feeding a BUFG and try to find a way to constrain the design properly.
Of course sun_ray is probably confusing ASICs with FPGAs and posted this in the wrong section.
Okay, but that is based on tools like DC, etc. This post is in the FPGA section, I have yet to see a tool Synplify, Leonardo, Vivado, ISE, Quartus, etc that will insert clock "gating cells" (which don't even exist in an FPGA) into a design based on having enables in your code. All of those primitives I mentioned have in Xilinx's own documentation for Inference: No and Instantiation: Recommended
If this was an ASIC tools question then it should have been posted in the ASIC section.
I think you should specify why you want clock gating cells in an FPGA design. It is possible that the code from jbeniston does what you want, but not with clock gating cells. FPGA tools will probably synthesize such code to a mux that feeds the output of the register back to it's input. The mux is controlled by the "clock gating" signal. It will have the same effect as clock gating, and if the mux logic fits inside the LUT it will cost nothing. The situation is different in ASIC design.
Do you want to mean that for ASIC synthesis if the rtl code has the enable in the rtl code as you showed in your rtl code at post no 2 , the synthesis tool will automatically insert clock gating cell? Does it mean that the rtl will have to have that enable for automatic clock gating cell insertion during ASIC synthesis? Does the rtl need to have anything more other than this enable for automatic clock gating cell insertion during ASIC synthesis?
Do you want to mean that for ASIC synthesis if the rtl code has the enable in the rtl code as you showed in your rtl code at post no 2 , the synthesis tool will automatically insert clock gating cell? Does it mean that the rtl will have to have that enable for automatic clock gating cell insertion during ASIC synthesis? Does the rtl need to have anything more other than this enable for automatic clock gating cell insertion during ASIC synthesis?
"Clock gating" is normally used to reduce power consumption by switching off the clock to some block of logic. You want to have control over this, so it should not be done automatically. Even if some tools can do it automatically, I don't see the point with testing the gate signal all over the place in the RTL source code. You will get in trouble if you forget the test somewhere. Keep the code clean and create a new (gated) clock, and instantiate the clock gating element manually.For ASIC designs, if several clocks have a common source and are gated in the same way, they can probably be considered to be in the same clock domain.
"Clock enable" works on individual registers and should be handled automatically, and the code should be written as suggested by jbeniston.
As a designer you normally don't care what the synthesis tool does with it. Almost all code is written like that. For ASIC design, leave the synthesis details to the "back end" people.
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