Help me fix code for divide by N counter

Hi,

Im looking for bit of help / advice!!!

Im desining a counter for a device and I am using flip flops to do so. Im
using a d-type flip flop then using that flip flop as a component for
other modules. The problem I am getting is when I use the flip flop as a
module I am not getting the output waveforms I am expecting. In fact Im
getting no waveforms!!

Here is the code for my flip flop:

entity dflipflop is
Port ( D : in std_logic;
Clk : in std_logic;
Q : out std_logic;
Q_bar : out std_logic);
end dflipflop;

architecture Behavioral of dflipflop is
begin
process(Clk)
begin
if (Clk'event and Clk = '1') then
Q <= D;
Q_bar <= not(D);

end if;

end process;
end Behavioral;

I then use that code as a component to generate a counter that will divide
by 2, 4, 8, and 16.

For example here is the code for my divide by 2 counter using the above
code as a component:

entity divide_by_two is
Port (Clk : in std_logic;
Clk_out : out std_logic);
end divide_by_two;

architecture Behavioral of divide_by_two is

component dflipflop is
Port ( D : in std_logic;
Clk : in std_logic;
Q : out std_logic;
Q_bar : out std_logic);
end component;

signal D : std_logic;
--signal F : std_logic;
begin

uuu: dflipflop port map(D,Clk,Clk_Out,D);

end Behavioral;

The code is compiling fine. After debuging the code I think the problem
is that my Q_bar is being equal to my D instead of the other way around
but I cannot seem to set D equal to Q_bar.

I am hoping that after looking at this for so long that it is in fact a
simple error on my part and any help would be greatly appreciated.

Please contact me at b00003716@[EMAIL PROTECTED]

Divide By N counter

Maybe you should instatiate your flip-flop like this:

signal D : std_logic;

uuu: dflipflop
port map(
D => not(D),
Clk => Clk,
Q => D,
Q_bar => open);

Clk_out <= D;

I don't think Q_bar is needed

Re: Divide By N counter

There is nothing wrong happening .. all ur mistake .

Take a look at your flip-flop, your filp flop does not have a reset or preset pin . For divide by 2 of clock , u connected the Q' pin of your flip flop to the D pin of your flip flop. This arrangement no doubt gives u a divide by 2 of clock . BUT ...BUT what happens on simulation ... initially Q' is uninitalized that is 'U' , so when clock is supplied to the flip flop your code passes 'U' to the 'D' input of your flipflop and so u have 'U" at the output . See if you want your circuit to work you should make sure that Q' pin of your flop should be in a known state ('0' prefreably since '1' will cause a phase shift) . The only way to make ur circuit work is to include a reset pin in ur filp flop code . Bring this pin out to your top entity . The circuit will work as soon as you release the circuit from reset.
Hope you understood , If not mail back

Re: Divide By N counter

Write the code for synchronous counter with n bit. Take the output at the each bit then you have divide by n bit. For example you have 4bit counter with clk input. then output at LSB will be Q0 = clk/2, Q1 = clk/4 and so on. Hope you understand what I say. Why you have to use individual D flip-flop? This is the idea, but in the real code you need to add rst input too.
T.L

Re: Divide By N counter

the tran said:

Write the code for synchronous counter with n bit. Take the output at the each bit then you have divide by n bit. For example you have 4bit counter with clk input. then output at LSB will be Q0 = clk/2, Q1 = clk/4 and so on. Hope you understand what I say. Why you have to use individual D flip-flop? This is the idea, but in the real code you need to add rst input too.
T.L

Click to expand...

Actually A2k s method is lot more effecient in terms of number of gates required because A2k will require 1 Flipflop for divide by 2 and 2 flipflop for divide by 4 , your method needs few more combinational gates also ... not that these numbers matter in todays design ... but just for the sake of argument ...yea what A2K is trying to do is OK ... i feel

Re: Divide By N counter

why vhdl to build a counter with dff "manually"!!!

in fact you should use the numeric_std library
and use these instructions:



process(raz,clk)
if raz='1' then qint <=(others=> '0');
elsif rising_edge(clk)
qint<= std_logic_vector(unstigned(dint)+1);
end if;
end process;
qout<=qint;

Re: Divide By N counter

I recently ran into problem of no signal change because of where I was probing the output signal.

Be sure you are looking at the logic chip's output, and not the output of an external drive transistor.