srikantamsravanthi
Newbie level 2
I am designing a circuit, there I have a requirement, AND gate open input should be considered as logic low and when one of the input is logic low other input shouldn't be passed to output.
Open input will happen because of some failure. Otherwise always two inputs are connected to AND gate.
To treat open input as logic zero, I have selected PECL(Positive Emitter Coupled Logic).
In 2 input AND, if one of the transistor fails at short then other input will be passed to output.
So when one of the input is open and corresponding transistor is failed at short mode then other input is passing to output.
To avoid this,any other logic family can I use or is there any other solution.
Open input will happen because of some failure. Otherwise always two inputs are connected to AND gate.
To treat open input as logic zero, I have selected PECL(Positive Emitter Coupled Logic).
In 2 input AND, if one of the transistor fails at short then other input will be passed to output.
So when one of the input is open and corresponding transistor is failed at short mode then other input is passing to output.
To avoid this,any other logic family can I use or is there any other solution.