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Multiple non-tristate drivers for net csal(3) in Elevador

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Hellsong

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I need help with the programation of and elevator, I'm traying to make a program to control a stepper-motor in order to make an elevator of 4 floors.
it works by pushing the button of the floor, and making a sequence to control the stepper-motor to make the elevator move to the floor it was required, and using proximity sensors to know where is the elevator, when the elevator is in front of one sensor, the output of the sensor is "0", it has 5 sensors for the 4 floors. here is the syntax of my program
Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity Elevador is
port( p1,p2,p3,p4,s1,s2,s3,s4,s5 :IN BIT;
    q   :OUT INTEGER RANGE 0 TO 7;
    csal    :OUT BIT_VECTOR (3 downto 0));
 
end Elevador;
 
architecture Elevador of Elevador is
begin
    piso1:PROCESS (p1)
    VARIABLE conteo :INTEGER RANGE 0 TO 7;
    BEGIN 
      IF (p1'EVENT AND p1 ='1') THEN
        IF (s1='0' AND s2='0') THEN conteo := 0;
        ELSE                conteo := conteo -1;
        END IF;
          q <= conteo; 
      END IF;           --PASO COMPLET0
            CASE conteo IS
            WHEN 0 => csal <= "1010";
            WHEN 1 => csal <= "1001";
            WHEN 2 => csal <= "0101";
            WHEN 3 => csal <= "0110";
            WHEN 4 => csal <= "1010";
            WHEN 5 => csal <= "1001";
            WHEN 6 => csal <= "0101";
            WHEN 7 => csal <= "0110";
        END CASE; 
    END PROCESS piso1;
 
    piso2:PROCESS (p2)
    VARIABLE conteo :INTEGER RANGE 0 TO 7;
    BEGIN 
      IF (p2'EVENT AND p2 ='1') THEN
        IF (s1='0' AND s2='0') THEN conteo := conteo +1;
        ELSIF (s2='0' AND s3='0') THEN conteo := 0;
        ELSE          conteo := conteo -1;
        END IF;
          q <= conteo; 
      END IF;           --PASO COMPLET0
            CASE conteo IS
            WHEN 0 => csal <= "1010";
            WHEN 1 => csal <= "1001";
            WHEN 2 => csal <= "0101";
            WHEN 3 => csal <= "0110";
            WHEN 4 => csal <= "1010";
            WHEN 5 => csal <= "1001";
            WHEN 6 => csal <= "0101";
            WHEN 7 => csal <= "0110";
        END CASE; 
    END PROCESS piso2;
 
    piso3:PROCESS (p3)
    VARIABLE conteo :INTEGER RANGE 0 TO 7;
    BEGIN 
      IF (p3'EVENT AND p3 ='1') THEN
        IF    (s1='0' AND s2='0') THEN conteo := conteo +1;
        ELSIF (s2='0' AND s3='0') THEN conteo := conteo +1;
        ELSIF (s3='0' AND s4='0') THEN conteo := 0;
        ELSE                conteo := conteo -1;
        END IF;
          q <= conteo; 
      END IF;           --PASO COMPLET0
            CASE conteo IS
            WHEN 0 => csal <= "1010";
            WHEN 1 => csal <= "1001";
            WHEN 2 => csal <= "0101";
            WHEN 3 => csal <= "0110";
            WHEN 4 => csal <= "1010";
            WHEN 5 => csal <= "1001";
            WHEN 6 => csal <= "0101";
            WHEN 7 => csal <= "0110";
        END CASE; 
    END PROCESS piso3;
 
    piso4:PROCESS (p4)
    VARIABLE conteo :INTEGER RANGE 0 TO 7;
    BEGIN 
      IF (p4'EVENT AND p4 ='1') THEN
        IF    (s4='0' AND s5='0') THEN conteo := 0;
        ELSE          conteo := conteo +1;
        END IF;
          q <= conteo; 
      END IF;           --PASO COMPLET0
            CASE conteo IS
            WHEN 0 => csal <= "1010";
            WHEN 1 => csal <= "1001";
            WHEN 2 => csal <= "0101";
            WHEN 3 => csal <= "0110";
            WHEN 4 => csal <= "1010";
            WHEN 5 => csal <= "1001";
            WHEN 6 => csal <= "0101";
            WHEN 7 => csal <= "0110";
        END CASE; 
    END PROCESS piso4;
end Elevador;

the problem I'm having is that, when I try to compile it, it shows these errors
Code VHDL - [expand]
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@E: CL219 :"C:\users\homero\documents\digital\elevador\elevador.vhd":9:1:9:4|Multiple non-tristate drivers for net csal(3) in Elevador
@E: CL219 :"C:\users\homero\documents\digital\elevador\elevador.vhd":9:1:9:4|Multiple non-tristate drivers for net csal(2) in Elevador
@E: CL219 :"C:\users\homero\documents\digital\elevador\elevador.vhd":9:1:9:4|Multiple non-tristate drivers for net csal(1) in Elevador
@E: CL219 :"C:\users\homero\documents\digital\elevador\elevador.vhd":9:1:9:4|Multiple non-tristate drivers for net csal(0) in Elevador
@E: CL219 :"C:\users\homero\documents\digital\elevador\elevador.vhd":8:1:8:1|Multiple non-tristate drivers for net q(2 downto 0) in Elevador
@E: CL229 :"C:\users\homero\documents\digital\elevador\elevador.vhd":8:1:8:1|Unresolved tristate drivers for net q(2 downto 0) in Elevador
@E: CL229 :"C:\users\homero\documents\digital\elevador\elevador.vhd":9:1:9:4|Unresolved tristate drivers for net csal(2) in Elevador
@E: CL229 :"C:\users\homero\documents\digital\elevador\elevador.vhd":9:1:9:4|Unresolved tristate drivers for net csal(3) in Elevador
@E: CL229 :"C:\users\homero\documents\digital\elevador\elevador.vhd":9:1:9:4|Unresolved tristate drivers for net csal(0) in Elevador
@E: CL229 :"C:\users\homero\documents\digital\elevador\elevador.vhd":9:1:9:4|Unresolved tristate drivers for net csal(1) in Elevador


if you could help me, I would be very glad, thanks and I'm waiting for you'r answers.

- - - Updated - - -

Also you should know that I'm traying to program this into a GAL22V10D
 

Attachments

  • Elevator.rar
    25.6 KB · Views: 84

You can't drive a signal from multiple processes. It's pretty obvious you're a software programmer trying to use VHDL. VHDL is a hardware description language if you can't draw a schematic of the hardware they you probably can't describe it correctly in VHDL.

I'm no expert on VHDL but I think the variable contero won't work as you expect when synthesized into hardware, seems to me the variable shouldn't even exist and the q should be in the if statement.

Do you have any idea how to use an FSM or write one? You should look it up and use one.
 
Thanks, I'm gonna loook into that and try to use it
 

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