VHDL Synthesis Code help

Hello,
I am using xilinx ISE 10.1, following is the code snippet.

u3rocess(samp_clk,eoc_adc)
Begin
if(samp_clk'event and samp_clk='1')then
conv_start<='0';
conv_start<='1'after 20ns;
if(eoc_adc'event and eoc_adc='1') then
cs_adc<='0';
rd<='0';
rd<='1' after 15ns;
cs_adc<='1' after 15ns;
end if;
end if;
end Process u3;
rd_adc<='0'when rd='0'else '1';

Click to expand...

It is not showing any errors but it is taking read,cs_adc as logic '1' always. It is displaying following warnings

-Register <conv_start> in unit <DPCM> has a constant value of 0 during circuit operation. The register is replaced by logic.
- Register <cs_adc> in unit <DPCM> has a constant value of 0 during circuit operation. The register is replaced by logic.
- Register <rd> in unit <DPCM> has a constant value of 0 during circuit operation. The register is replaced by logic.
WARNING:Xst:647 - Input <eoc_adc> is never used.

Click to expand...

My design is when adc gives active low eoc ,after that when it returns again to logic'1' then we should send read signal for 10ns.That is why I have written in that way,Is there any other correct way.
Thank you.

ISE is a synthesis tool and ignores any simulation timing statements. To generate timing in hardware, you need an input clock and sequential statements referring to it.

FvM the OP has a clock samp_clk.

The problem is they are using both the unsynthesizable after clause and they have another "clock" (eoc_adc) embedded inside the if statement for the samp_clk. Not sure what hardware that is supposed to describe, but it certainly doesn't exist anywhere on this planet.

Looking at your past posts I don't think you've taken the time to learn VHDL from a good modern BOOK. You are treating VHDL as if it was a procedural software language. Well it's not a procedural language so don't code as if it is such.

I can tell you are expecting that the rising edge of the sample clock will "trigger" the procedural steps you specified:
set conv_start to 0
set it to 1 20ns later
then wait for a rising edge of eoc_adv
set cs_adc and rd to 0
set rd and cs_adc to 1 15ns later (not sure if this was the intent or cs_adc 15ns after the rd)

You might be able to get away with this in a testbench (which you aren't synthesizing) but you can't do this in synthesizable code as it doesn't represent any kind of hardware.

1. Have 2 process blocks: one for checking samp_clk and the other for checking eoc_adc.
2. Determine these time periods(15 & 20 ns) in terms of number of "respective clocks".
3. Run counters to count up to these number of "respective clocks".
4. Set flags after these events.
5. Check these flags and then generate cs_adc, conv_start and rd.
6. Use rising_edge function instead of checking clk=1 and clk'event.
7. Pick up a good book to read about writing synthesizable code.

I have modified my code this way
It has not given those warnings.

u3rocess(samp_clk)
Begin
if(rising_edge(samp_clk))then
conv_start<='0','1' after 15ns;
end if;
end Process u3;
rd<=eoc_adc after 15ns;
cs<=eoc_adc after 15ns;
rd_adc<=rd;
cs_adc<=cs;

Click to expand...

will this work good after dumping into FPGA.
What is the difference in using rising_edge function and clk'event and clk='1'

Can I ignore the warning
WARNING:Xst:646 - Signal <diff<11:4>> is assigned but never used.

In this code, conv_start will always be zero on the fpga as after statements are only meant for simulation.

For good fpga code, remove the after statements.

Rising edge is more appropriate as it can prevent some odd simulation situations but won't affect synthesis. But roasting edge reads better in the code, so I recommend sticking with it.

It looks like you are missing a text book like "VHDL for hardware design" or similar.

As previously stated, none of the testbench/simulation timing statements works for hardware synthesis.

You need to think your design in terms of synthesizable elements, flip-flops and combinational logic. Use a synchronous scheme with a single input clock that drives all flip-flops. Complex sequences can be best described as state machines.

I need to give conv_start only for 15ns after rising_edge(clk)
how to write in synthesis

Y.SAI SARASWATHI said:

I need to give conv_start only for 15ns after rising_edge(clk)
how to write in synthesis

Click to expand...

It has to be set conv_start = '1' then cleared conv_start <= '0' based on the period of some clock (i.e. set on one clock cycle (state?) and cleared on the following clock cycle (another state?)). Do you understand what was meant by "Complex sequences can be best described as state machines."? In other words you should probably use an FSM to perform the proper timing of the signals and use a clock that has a period of 15ns (if that is the requirement).

You can have an FSM or you could do what I have described under step3 above. Let me explain.Assuming you have a clock period of 5 ns, you can run a counter for 3 clocks(getting 15 ns). Once the counter reaches 3, set a flag and then check this flag to set rd or conv_start (or whatever...)

I think from a newbie perspective coming from a software background using an FSM might be easier for them to understand, then again I could be wrong and they will comprehend the flag approach better. Regardless they need to get rid of the after clauses so the code can represent actual hardware.

Y.SAI SARASWATHI said:

I need to give conv_start only for 15ns after rising_edge(clk)
how to write in synthesis

Click to expand...

There is NO SUCH thing as 'after 15ns;' in Verilog or VHDL code to be loaded onto an FPGA.
Such 'code' can ONLY be used for TESTING and SOFTWARE simulation, it WILL NOT WORK inside an FPGA, even if it compiles with no errors.

(Think of it this way… HOW can the FPGA know what 15ns is?, it cannot…. YOU need to tell it HOW to measure 15ns )


1. find out your system clock into the FPGA.
2. write a counter that counts the same number of system clock cycles' to make up 15ns and triggers a flag.
3. use THAT flag to trigger the start of your conversion, then do the same for the stop functionality.

Indeed. Use for example a 200 MHz clock, then 3 counts is your 15 ns interval.