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do functions synthesize to combinational logic?

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shainky

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hi,
I have a module which is such that

Code: 
module code3b (o, a, nrst, en);
output o;
input a, nrst, en;
reg o;
always @(a or nrst or en)
o = latch(a, nrst, en);
function latch;
input a, nrst, en;
if (!nrst) latch = 1'b0;
else if (en) latch = a;
endfunction
endmodule

Will this infer a latch or a combinational logic, as I have a function which is defining the output.
if combinational logic, what kind of logic would it be?

Thanks.
 
Last edited by a moderator:

You should have gotten a synthesis error from this because your function does not make a return value assignment in all possible statement branches of the function.
Consider this modified example(also showing Verilog-2001 port syntax)

Code: 
module code3b (output reg o1, o2,
                      input a1, a2, nrst, en);
  always @(a1 or nrst or en)
       o1 = latch(a1, nrst, en);
  always @(a2 or nrst or en)
       o2 = latch(a2, nrst, en);
  function latch(input a, nrst, en);
    if (!nrst) latch = 1'b0;
       else if (en) latch = a;
  endfunction
endmodule
By default in Verilog, function arguments and return variables are static. There is only one latch variable shared for all invocations of the function. So if en is not true, the value of latch depends on which call to latch() was the last to set it. In Verilog-2001 and SystemVerilog, you now have the option of making the function automatic, which implicitly declares the function arguments and return variables as automatic. The initial value of latch return value is X, so synthesis will treat it as a combinatorial dont care.
 
Hi,

Functions are synthesizable.
The above code will synthesize to latch because you are not defining the output when en == 1'b0. So when en is 1'b0, it will give previous value when en == 1'b1, which is a latch.

Hope this helps!
 

sivateja.m said:
Hi,

Functions are synthesizable.
The above code will synthesize to latch because you are not defining the output when en == 1'b0. So when en is 1'b0, it will give previous value when en == 1'b1, which is a latch.

Hope this helps!
Click to expand...
Except that the "previous value" is not what you would always expect. That is why it will not simulate correctly and should be a synthesis error.
 

Hi Dave

"Except that the "previous value" is not what you would always expect. That is why it will not simulate correctly and should be a synthesis error."

Can you explain in more detail please ?
 

Look at my example above. There is only one static variable to save the state of the two latches. Try simulating with the testbench below and see what values out get for out1 and out2.
Code: 
module top;
wire out1, out2;
reg in1, in2;
reg en,rstb;

code3b u(out1, out2, in1,in2,rstb,en);
initial begin
   rstb=1;
   en = 1;
   $monitor($time,, out1,, out2,, in1,,in2,,rstb,,en);
   in1 = 0;
   in2 = 1;
   #1;
   en = 0;
   #1;
   in1 = 1;
   in2 = 0;
   #1;
   en = 1;
   #1;
   en = 0;
   #1;
   in1 = 0;
   in2 = 1;
   #1;
     $finish;
end
endmodule
 

dave_59 said:
By default in Verilog, function arguments and return variables are static. ... In Verilog-2001 and SystemVerilog, you now have the option of making the function automatic, which implicitly declares the function arguments and return variables as automatic.
Click to expand...

Useful reminder! Thanks. :)
 

Why was this thread moved? ASIC or FPGA is irrelevant.
Click to expand...
It's in fact irrelevant for the topic of this thread. There's no general VHDL or Verilog section at Edaboard. Habitually general HDL questions as well as elementary hardware synthesis related questions are posted in the FPGA forum while the ASIC forum is dedicated to gate level synthesis and other specific ASIC related problems.

In my view it makes sense to move basic HDL questions to the FPGA section, but regularly a thread shouldn't be moved after the first replies.
 

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