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VHDL code for the gate circuit

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kongruxue

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Hi, I want to get the gate circuit which shows in the handwrite gate circuit gate_circuit.JPG.
so I wrote the VHDL code below
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY memory_cell IS
PORT
	( I          :IN  std_logic;----input bit
	  W          :IN  std_logic;-----write_enable
	  S          :IN  std_logic;----select_enable
	  clk        :IN  std_logic;
	  q          :OUT std_logic------output bit
	  );
END memory_cell;
ARCHITECTURE structural OF memory_cell IS
SIGNAL J,K,J_g,K_g,Qa,Qb :std_logic;
ATTRIBUTE keep : boolean;
ATTRIBUTE keep OF J_g,K_g,Qa,Qb: SIGNAL IS true;
BEGIN
K <= NOT I AND W AND S;
J <= I AND W AND S;
K_g <= NOT (K AND clk AND Qa);
J_g <= NOT (J AND clk AND Qb);
Qa <= K_g NOR Qb;
Qb <= J_g NOR Qa;

q <= Qa;
END structural;

and I check the RTL Viewer, I get the image
memory_cell.png

but not the same, How do I change the code?
 

All of your assignments are outside of a process so they are implemented in combinatorial logic.

If you want logic to only run on a clock edge, either rising or falling, you should create a clocked process like the following:

Code: 
process (clk, rst)
begin
  if (rst = '0') then
    K_g <= '0';
  elsif rising_edge(clk) then
    K_g <= not (K and Qa);
    etc...
  end if;
end process;

You could remove the reset assignment, but somewhere you should initialize the logic so X's don't propagate through the design.
 
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    TuAtAu

    TuAtAu

    Points: 2
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Gbounce, I think the point here is to CREATE a flip-flop from gates, not just INFER a f-f. With that said, I haven't sat down
and analyzed the two circuits and why they're different (or if they actually are from a functional point of view)
 

Thanks. like Barry said. I want to create a flip-flop from gates. I want the gate circuit exactly the same which shows in the first image. where and how should i change the code to get it? PS .i wrote all codes from gates,so I don't use process.
 

the synthesisor will minimise the gates into something that is functionally identical. you wont be able to stop it. but if you test it it should work identicallty
 

To refer to some comments, the circuit doesn't represent a clock edge sensitive synchronous FF description, and there's no change to infer a FF from it, what ever you do with it.

Second comment, if you want to behave it as level clocked FF, the implementation details can actually matter. We need to ask for the target hardware. If it's FPGA synthesis, there are no real "gates" at all, and all expectations of a particular gate specific behaviour may be void. In return, a FPGA synthesis tool isn't prepared for synthesizing gate structures. An ASIC tool however is.

As TrickyDicky said, the synthesized RTL circuit has apparently the same (statical) logic behaviour. There's a principle option, to assign logic nodes to real logic element by vendor specific synthesis attributes or low level primitives. So you can make the RTL more look like your original circuit. But a FPGA implementation still involves routing delays and possibly glitches of switching logic elements, that aren't present in real gates.
 

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