Cannot continue because of fatal error.

Hi all;

I write a VHDL code below. There are no error when I compile it in Quartus, but then fatal error occur when I try to simulate in ModelSim.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity LUT_h1 is
port(
address : in std_logic_vector(7 downto 0);
result : out std_logic_vector(8 downto 0)
);
end LUT_h1;

architecture behavioral of LUT_h1 is
type LUT is array(0 to 3) of std_logic_vector(8 downto 0);
constant lut_h1calc : LUT := (
"000000000",
"000000000",
"000000000",
"000000001");

begin
process(address)
variable address_int : std_logic_vector (7 downto 0);
begin
address_int := address;
result <= lut_h1calc(conv_integer(address_int));
end process;
end behavioral;

configuration config_lut_h1 of LUT_h1 is
for behavioral
end for;
end config_lut_h1;
----------------------------------------------------------------------------------------------------
This is the error occur in ModelSim.

# Cannot continue because of fatal error.
# HDL call sequence:
# Stopped at H:/altera/LUT_h1_tb/LUT_h1.vhd 26 Process line__22

What is my mistake..anyone help me please..Thank you.

no problems here

---------- Post added at 12:14 ---------- Previous post was at 12:12 ----------

where is your testbench code?

Hi TrickyDicky,

This my testbench code:
--------------------------------------------------------------------
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity LUT_h1_tb is
end;

architecture bench of LUT_h1_tb is

component LUT_h1
port(
address : in std_logic_vector(7 downto 0);
result : out std_logic_vector(8 downto 0)
);
end component;

signal address: std_logic_vector(7 downto 0);
signal result: std_logic_vector(8 downto 0) ;

begin

uut: LUT_h1 port map ( address => address,
result => result );

stimulus: process
begin

address <= "01110111";
wait for 20ns;

address <= "11110000";
wait for 20ns;

address <= "00001111";
wait for 20ns;

wait;
end process;
end;

Thanks for reply

You missed the important bit out of the error.

# ** Fatal: (vsim-3734) Index value 119 is out of range 0 to 3.

The problem is the LUT only has addresses 0 1 2 3, and you try to access address 119 that doesnt exist.

Hi TrickyDicky,

Sorry for the stupid error for me. Actually, I try to understand the LUT concept based on the code above.
What I can see is the output will access the input address. Can you explain more on LUT?
Thanks for reply

---------- Post added at 14:05 ---------- Previous post was at 13:07 ----------

LUT is used to store any values...
How can I store a value in LUT and later can access the value?

In that case, its not a lut, it is a memory.

I would read up on synthesis templates for rams.