Victory1981
Newbie level 6
A Process statement can be synthesised into combinational circuit and sequential circuit. Is there any general rule to determine which kind of circuit it will be synthesised into?
An example:
p1rocess(Clock)
Begin
If rising_edge(Clock) then
Case State Is
When S0=>
If XXXX then
State<=S1;
End If;
When S1=>
If XXXX then
State<=S2;
End If;
...
End Case;
End If;
End;
p2rocess(State)
Begin
Case (State)
When S0=>
Output<=XXX;
When S1=>
Output<=XXX;
...
End Case;
End Process;
p1 was synthesised into sequential circuit while p2 was combination circuit.
Why? Is there any general rule?
Thank you.
An example:
p1rocess(Clock)
Begin
If rising_edge(Clock) then
Case State Is
When S0=>
If XXXX then
State<=S1;
End If;
When S1=>
If XXXX then
State<=S2;
End If;
...
End Case;
End If;
End;
p2rocess(State)
Begin
Case (State)
When S0=>
Output<=XXX;
When S1=>
Output<=XXX;
...
End Case;
End Process;
p1 was synthesised into sequential circuit while p2 was combination circuit.
Why? Is there any general rule?
Thank you.