Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

clock generator using ramp with VH and VL

Status
Not open for further replies.
A

allennlowaton

Full Member level 5
Joined
Oct 5, 2009
Messages
247
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,298
Location
Taiwan
Activity points
3,063
Hello everybody,

Please help me with this.
I'm doing a clock generator from a ramp and the figure is shown below.
My concern is although using the circuit I was able to obtain a 1MHz from a VDD=2.7~5.5V,
the resulting ramp is not within the VH and VL limit. Am I doing the right track?

Shown below are the resulting simulations..

.

Thank you for taking time reading this one.

---------- Post added at 08:57 ---------- Previous post was at 08:56 ----------

I'm using VH = 1.2V and VL = 0.6V
 

It is caused by comparator delay. In silicon, comparator offset will also lead to difference.
For the valley, this structure could not be equal to VL. The discharging is so fast.
 
leo_o2 said:
It is caused by comparator delay. In silicon, comparator offset will also lead to difference.
For the valley, this structure could not be equal to VL. The discharging is so fast.
Click to expand...

I don't understand why the lower limit of the Vramp goes down to negative.
 

When NMOS M7 is turned off, its channel charge will be injected to Cramp. Carrier in M7 is electron that carries negative charge.
 
leo_o2 said:
When NMOS M7 is turned off, its channel charge will be injected to Cramp. Carrier in M7 is electron that carries negative charge.
Click to expand...

All I need is the clock pulse with 50% duty cycle. I really don't know what is the expected graph for the vramp.
 

If so, you don't care much about the ramp signal. 50% duty cycle can be achieved by d-flipflop.
 
  • Like
Reactions: allennlowaton

    V

    Points: 2
    Helpful Answer Positive Rating
    A

    allennlowaton

    Points: 2
    Helpful Answer Positive Rating
If i want a variable duty cycle clock, I can use a ramp generator and a comparitor with variable reference right?? In that case, how lower a frequency can I go to?? I want to generate a clock which has a frequency that can vary from 1-60Hz with duty cycle variable..is it possible by this method in IC??? The frequency is very low, that is why I am asking...any other way you suggest...

thanks
 

Of course, you can do it. However the capacitor for ramp should be very big.
Even the ramp can be generated in digital way.
 

How do you generate the ramp in a digital way..any circuits that can do that???any references????....thanks
 

I mean the ramp signal can increase step by step thru digital control.
 
thanks..............................................................
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top