jimmy_tag
Member level 2
I am a beginner in VHDL.
I have designed a Counter form 0 to 9 and displaying it on 7 seg.
For delay i used the simple loop statement from 0 to 50000...
my code is written below..
My problem is when i am trying to compile code it dont found any errors it just keep doing analysis and no compilation is done.. i compiled some simple programms they are working good... i dont know whether it is a problem of code or what...
( I am using quartus 9.2)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(
clk,rst : in std_logic;
op: out std_logic_vector (6 downto 0));
end counter;
architecture count of counter is
begin
process(clk,rst)
variable m : std_logic_vector (3 downto 0) :="0000";
constant max: integer:=50000;
variable cot: integer:=00000;
variable flag: std_logic;
begin
while rst /= '0' loop
loop
if (clk'event and clk='1') then
cot:=cot+1;
end if;
exit when cot=max;
end loop;
flag:='1';
if m="1010" then
m:="0000";
elsif flag='1' then
m := m + 1;
end if;
if(m="0000") then
op<="1000000";
elsif(m="0001") then
op<="1111001";
elsif(m="0010") then
op<="0100100";
elsif(m="0011") then
op<="0110000";
elsif(m="0100") then
op<="0011001";
elsif(m="0101") then
op<="0010010";
elsif(m="0110") then
op<="0000010";
elsif(m="0111") then
op<="1111000";
elsif(m="1000") then
op<="0000000";
elsif(m="1001") then
op<="0010000";
else
op<="1111111";
end if;
flag:='0';
end loop;
end process;
end count;
I wiil be great if i get help...
also i didnt understand what there is diffrence in code between testbench modelling and hardware modelling...
i am using J.Bhaskar(VHDL Primer)
any other good book for hardware modelling in VHDL. or VHDL example book?
I have designed a Counter form 0 to 9 and displaying it on 7 seg.
For delay i used the simple loop statement from 0 to 50000...
my code is written below..
My problem is when i am trying to compile code it dont found any errors it just keep doing analysis and no compilation is done.. i compiled some simple programms they are working good... i dont know whether it is a problem of code or what...
( I am using quartus 9.2)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(
clk,rst : in std_logic;
op: out std_logic_vector (6 downto 0));
end counter;
architecture count of counter is
begin
process(clk,rst)
variable m : std_logic_vector (3 downto 0) :="0000";
constant max: integer:=50000;
variable cot: integer:=00000;
variable flag: std_logic;
begin
while rst /= '0' loop
loop
if (clk'event and clk='1') then
cot:=cot+1;
end if;
exit when cot=max;
end loop;
flag:='1';
if m="1010" then
m:="0000";
elsif flag='1' then
m := m + 1;
end if;
if(m="0000") then
op<="1000000";
elsif(m="0001") then
op<="1111001";
elsif(m="0010") then
op<="0100100";
elsif(m="0011") then
op<="0110000";
elsif(m="0100") then
op<="0011001";
elsif(m="0101") then
op<="0010010";
elsif(m="0110") then
op<="0000010";
elsif(m="0111") then
op<="1111000";
elsif(m="1000") then
op<="0000000";
elsif(m="1001") then
op<="0010000";
else
op<="1111111";
end if;
flag:='0';
end loop;
end process;
end count;
I wiil be great if i get help...
also i didnt understand what there is diffrence in code between testbench modelling and hardware modelling...
i am using J.Bhaskar(VHDL Primer)
any other good book for hardware modelling in VHDL. or VHDL example book?