dionysian
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I am having an issue with creating and using a Xilinx core I generator using the core generator. My issue is when I add a core to my project (this case a cordic core) and I attempt to implement my design I get an error in the translate process that is shown below:
ERROR:NgdBuild:604 - logical block 'U0' with type 'wrapped_cordic' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'wrapped_cordic' is not supported
in target 'spartan3'.
My code where I try to use this code is shown below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
Library XilinxCoreLib;
entity cordic_test_top is
port (
phase_in: IN std_logic_VECTOR(15 downto 0);
x_out: OUT std_logic_VECTOR(15 downto 0);
y_out: OUT std_logic_VECTOR(15 downto 0);
rdy: OUT std_logic;
clk: IN std_logic);
end cordic_test_top;
architecture Behavioral of cordic_test_top is
component wrapped_cordic
port (
phase_in: IN std_logic_VECTOR(15 downto 0);
x_out: OUT std_logic_VECTOR(15 downto 0);
y_out: OUT std_logic_VECTOR(15 downto 0);
rdy: OUT std_logic;
clk: IN std_logic);
end component;
begin
U0 : wrapped_cordic
port map (
phase_in => phase_in,
x_out => x_out,
y_out => y_out,
rdy => rdy,
clk => clk);
end Behavioral;
Now the error message says that it might be a pin name misspelling ( I doubt that) a missing edif or ngc file. Now I notice a ngc file was created when the core was generated and I don’t think I have to explicitly add this to my file. Does anyone have suggestion on how this may work?
ERROR:NgdBuild:604 - logical block 'U0' with type 'wrapped_cordic' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'wrapped_cordic' is not supported
in target 'spartan3'.
My code where I try to use this code is shown below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
Library XilinxCoreLib;
entity cordic_test_top is
port (
phase_in: IN std_logic_VECTOR(15 downto 0);
x_out: OUT std_logic_VECTOR(15 downto 0);
y_out: OUT std_logic_VECTOR(15 downto 0);
rdy: OUT std_logic;
clk: IN std_logic);
end cordic_test_top;
architecture Behavioral of cordic_test_top is
component wrapped_cordic
port (
phase_in: IN std_logic_VECTOR(15 downto 0);
x_out: OUT std_logic_VECTOR(15 downto 0);
y_out: OUT std_logic_VECTOR(15 downto 0);
rdy: OUT std_logic;
clk: IN std_logic);
end component;
begin
U0 : wrapped_cordic
port map (
phase_in => phase_in,
x_out => x_out,
y_out => y_out,
rdy => rdy,
clk => clk);
end Behavioral;
Now the error message says that it might be a pin name misspelling ( I doubt that) a missing edif or ngc file. Now I notice a ngc file was created when the core was generated and I don’t think I have to explicitly add this to my file. Does anyone have suggestion on how this may work?