Kekkaishi
Member level 1
VHDL on Apex20K
Hello to all,
I’m newbie in VHDL programming on FPGA. I need help from all of you out there. Right now I try to write a code for 2-digit BCD down Counter, LCD display message and synchronization between both of them.
For 2-digit BCD down counter, here’s my code
for the code above I need to make it start from 60, 30 and 10 and then be counted down to 0. Both bits should work together, I mean like form 60,59,58,57…… but I can’t configure it how to do it.
I’m currently using Nios Development kit.
Hope someone can help me. Thank you.
Hello to all,
I’m newbie in VHDL programming on FPGA. I need help from all of you out there. Right now I try to write a code for 2-digit BCD down Counter, LCD display message and synchronization between both of them.
For 2-digit BCD down counter, here’s my code
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity bcdcounter1 is
port (
RST : in std_logic;
Digit1_O : out unsigned(3 downto 0);
Digit2_O : out unsigned(3 downto 0);
CLK : in std_logic
);
end bcdcounter1;
architecture bcdcounter1_arch of bcdcounter1 is
signal Digit1 : unsigned(3 downto 0);
signal Digit2 : unsigned(3 downto 0);
begin
process (CLK,RST)
begin
if RST = '0' then
Digit1 <= (others=>'0');
elsif rising_edge(CLK) then
if Digit1 > 0 then
Digit1 <= Digit1 - 1;
else
Digit1 <= (others=>'0');
end if;
end if;
if RST = '0' then
Digit2 <= (others=>'0');
elsif rising_edge(CLK) then
if Digit2 > 0 then
Digit2 <= Digit1 - 1;
else
Digit1 <= (others=>'0');
end if;
end if;
end process;
Digit1_O <= Digit1;
end bcdcounter1_archfor the code above I need to make it start from 60, 30 and 10 and then be counted down to 0. Both bits should work together, I mean like form 60,59,58,57…… but I can’t configure it how to do it.
I’m currently using Nios Development kit.
Hope someone can help me. Thank you.
