What is a clock jitter and when does it occur?

what is a clock jitter and when it arrives :?:

Re: clock jitter

Jitter is defined the short-term variations (long-term or slow variations are called wander) of the significant instants of a digital signal from their ideal positions in time. In case of a clock next rising or falling edge may come after or before the accuate cycle time..

There can be many reasons inlcuding power supply variations, switching noise, cross-talk.. Random (gaussian) jitter due to temperature variations and semicinductor dopping variations in devices.

Re: clock jitter

Read this article from Cypress Semiconductor to learn more about timing problems and techniques.

https://www.cypress.com/cfuploads/support/app_notes/perfecttiming.pdf

Re: clock jitter

This EEDesign article
"Phase noise and jitter -- a primer for digital designers" is also good.

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Re: clock jitter

Clock jitter : There are cycle to cycle variations from the normat (t=1/F) timings of the source clock. These variations are not predictable and may depend on many factors. This behaviour is termed as Jitter and are very important for the design. This is also related to the phase noise of the clock.

Phase noise/Clock jitter is important both for analog and digital design. In analog it decides the bandwidth of various components and in digital the maximum speed (provided the other devices do not have any timing constraint)

Re: clock jitter

Absolute jitter is defined are the deviation in zero crossing instances from a perfect clock. This type of jitter has a growing variance. It is not so important in communication systems.

Cycle-to-cycle jitter is the period variation for one cycle compared to the perfect period (not to the next period). (by the way, some people also call it cycle jitter which is perhaps more expressive) Under white noise, these samples are uncorrelated. This type of jitter can be easily related to phase noise in time references and is crucial in all clock and and data recovery applications.

Subject to flicker noise, there is no exact analysis but some approximate formulas do exist.

In a locked loop, jitter keeps on accumulating for a period of time on the scale of the loop time constant then feedback can correct for any slower variations leading to constant amount of jitter.

Colombo2

Re: clock jitter

thanks for the reply

does any combinational logic in the clock path cause jitter..suppose i want to select one among three clock and use a simple mutliplexer...(avoided clock glitch)....will there be any jitter in the output clock...

thanks

Re: clock jitter

combinational logic does not cause "clock jitter" but can cause glitches. In the xample of selecting one of the three clocks there will be no clock jitter if the selection is one time. However if you switch amongst the clocks many times and this switching is not synchronized there shall be glitches.

The glitches may be avoided using some redundancy

Re: clock jitter

Combination logic for clock selection introduces glitches and skew which may affect the circuit considerably. Which device are you using? Xilinx devices have dedicated multiplexers for multiplexing clocks which will solve your problem. I am not sure about @ltera devices.

Re: clock jitter

it_boy said:

Combination logic for clock selection introduces glitches and skew which may affect the circuit considerably.

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hi
i think clock skew and glitches have no problem with my desiign,,,

glitches can be avoided by taking care in switching...and skew has no problem since FPGA gives out the reference clock

.i was considered whether any jitter would be produced..and i feel there should be no jitter...

and that document "perfect tiiming" is really very useful

thanks for all the help

Re: clock jitter

it_boy said:

Combination logic for clock selection introduces glitches and skew which may affect the circuit considerably. Which device are you using? Xilinx devices have dedicated multiplexers for multiplexing clocks which will solve your problem. I am not sure about @ltera devices.

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What are the dedicated MUXs for Clock Muxing you are talking about in Xilinx devices. Can you explain this further?

Thanks
Kode

Re: clock jitter

Actually, cominational logic or even simple inverters can add jitter to the clock. If you buffer the clock with a chain of inverters, each inverter has its own input referred noise. This noise adds to the clock and alters the zero-crossing moment accordeing to the first-crossing-time jitter model. Therefore, jitter keeps on accumulating in the chain. The amount of jitter added per inverter is small but the amount you can tolerate depends indeed on your application.

Colombo2

Re: clock jitter

xfpgas said:

What are the dedicated MUXs for Clock Muxing you are talking about in Xilinx devices. Can you explain this further?

Thanks
Kode

Click to expand...

Check the following link for a simple explanation. Search xilinx for details.
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