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Blocked and Distributed Ram inference in xilinx fpga

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Hi all,

Why in xilinx the blocked Ram and the Distributed Ram are infered when the READ_ADD is registerd (blocked RAM) and when not registerd it will be infered as Distributed RAM.

Thanks
Kil
 

The Xilinx Block RAM in silicon has a permanent address input register that cannot be bypassed. It other words, Block RAM can't do asynchronous reads. If your HDL doesn't include a similar register, then the synthesis tool can't use a Block RAM, and must fall back to using Distributed RAM.
 

echo47 said:
The Xilinx Block RAM in silicon has a permanent address input register that cannot be bypassed. It other words, Block RAM can't do asynchronous reads. If your HDL doesn't include a similar register, then the synthesis tool can't use a Block RAM, and must fall back to using Distributed RAM.
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I have coded my VHDL so as to have a register array that is 32deep X 42bits .. The problem I'm facing is that when running XST, this only code takes around 5 hours of synthesis/optimization !! .. and I get this warning:
You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time
Click to expand...

What could be the reason for this long synthesis time ? ..
 

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