How to make an use a memory table in VHDL?

Memory table in vhdl

Hello everyone,

So i have to design a communication module that will have some inputs and outputs and will connect more components from de same sistem(i have a sistem that will be divided and i have to rezolv the communication between them). so every component will be conected to a comm. module with the inputs and outputs, and i have to make a table, a memory that will keep the corespondence between what input coresponds to what component and at what output.i don't know how can i make this in vhdl, this table and then how to use it.
i hope i made myself clear.
thank you!
Oana

Re: Memory table in vhdl

A lot is missing for a clear question. What kind of communication channel is used for send and receive by each component? Are they using point to point connections or a bus? Your communication module is intended as a kind of hub or router. Does each module send and receive different messages (with an indentifier or an address), that have to be routed individually? Or does it send identical, composite messages, that to have be split in parts for different receivers?

Re: Memory table in vhdl

Yes, i thought i was not clear.
So for sending and receiving the messages i will use an UART, so point to point communication. So, for example, the communication module will receive a message from UART and it will verify if the destination address is his, if it is, it will dissasembly the message and it will send only the data forward to the component. I do not know if this communication module is intended as a router or as a hub, i never thought of things that way... a router is smarter, but i just have to send and receive messages, check if it is for me and if not, put on the queue for sending forward on the network(that is also a problem in the sense that i don't know exactly how to do it, i have to implement some kind of queue for sending, because there might be more messages to be send in the same time) and assembly and dissasembly messages. About the messages, they can be send and received by all the modules, when a module sends a message, this message contains the source address, destination address, the data and a CRC(something like this, i have to decide on the structure of the message) and this message will travel through all the network and it will stop at the module that recognizes his address.
I would like to make a schematics, i have to make some time for that, but i thing it would be easier in understanding this system.
Thank you a lot for you interest in my problem!!

Re: Memory table in vhdl

I don't see clearly what's the purpose of central communication module in the topology you sketched now. If messages have full addresses, they can be basically distributed in a multi-master bus system, as done e. g. in PROFIBUS or IP networks.

Re: Memory table in vhdl

Well the project is part of a bigger one related to Petri nets, that was not the point, it's not about central or distributed communication....
my question was how to make a memory table in vhdl, something that only keeps teh relation between modules, between their inputs and outputs......
thanks anyway.........