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Modelsim - how to reset flip-flops ?

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Hello,

I have one question.
I would like to simulate a design in Modelsim. The design is not yet finished and the global reset is not implemented.
Is there any possibility how to reset all flip-flops at the beginning of the simulation to default "0" value ?
 

Perhaps I am not understanding, but I guess that you have developed some logic that will be reset by a global signal and you still have not design the logic for the reset. Is it Ok?
If this is your case, you can force the signal with Modelsim with a command or using the user interface, or create a behavioral description of your future reset logic or just a signal in your testbench.

Hope it helps.
 

Yes, you are right.

I have a design, which will be synthesised in Xilinx CPLD. Those CPLDs have a global reset.
But now, I need to do a functional simulation of the part of the design.
For the simulation, I am using a testbench, where is the design and some behavioral models (FLASH ROM etc.).
I need to set all FFs in my design to the known state (0) at the start of simulation.¨
In the final hardware implementation, this will be done via global reset.
But how I can do it in simulation ? I browsed the Modelsim manual, but I did not found any command like "reset all FFs to 0".
 

One way to ensure everything is at '0' is to initialize all your internal signals to their default value. I do that sometimes when I don't want a global reset signal since all FFs are '0's at power-up.

signal junk1: std_logic := '0';
signal junk_bus: std_logic_vector (10 downto 0) := (others=>'0');

However, I thought that you had to provide a reset signal to all your vhdl modules in order to use the xilinx global reset. If each FF in your module does not have a reset, how can the global reset be used? Does the xilinx tool do it by default?

TurboPC
 

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